Abstract: A "virtual FIFO" system for use in buffering data between transacting buses that transfer data at different rates includes a memory device and a controller that partitions the memory device into multiple regions, each of which is configured to operate as a distinct data buffer.

Abstract: An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.