Patents by Inventor Dan Tomescu
Dan Tomescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7908461Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: GrantFiled: December 19, 2007Date of Patent: March 15, 2011Assignee: Allsearch Semi, LLCInventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20080307196Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: ApplicationFiled: May 28, 2008Publication date: December 11, 2008Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Patent number: 7451293Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: GrantFiled: October 19, 2006Date of Patent: November 11, 2008Assignee: Brightscale Inc.Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Patent number: 7383421Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: GrantFiled: December 4, 2003Date of Patent: June 3, 2008Assignee: Brightscale, Inc.Inventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20080126757Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: ApplicationFiled: December 19, 2007Publication date: May 29, 2008Inventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20070130444Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: ApplicationFiled: October 19, 2006Publication date: June 7, 2007Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Patent number: 7107478Abstract: A data-processing system includes a data device for selectively storing data and an engine having access to the memory device, the engine supporting a plurality of machine executable programs. A controller is utilized which selectively outputs one of a plurality of instructions to the engine for driving the execution of the programs enabled by the engine, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the data device, the engine and the controller. The controller outputs one of the instructions to the engine for execution of one of the programs, while also executing an operation within itself, all within a single clock cycle.Type: GrantFiled: December 4, 2003Date of Patent: September 12, 2006Assignee: Connex Technology, Inc.Inventors: Dan Tomescu, Gheorghe Stefan
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Patent number: 7069386Abstract: An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.Type: GrantFiled: May 10, 2004Date of Patent: June 27, 2006Assignee: Connex Technology, Inc.Inventors: Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu
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Publication number: 20040210727Abstract: An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.Type: ApplicationFiled: May 10, 2004Publication date: October 21, 2004Applicant: GEMICER, INC.Inventors: Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu
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Publication number: 20040123073Abstract: A data-processing system includes a data device for selectively storing data and an engine having access to the memory device, the engine supporting a plurality of machine executable programs. A controller is utilized which selectively outputs one of a plurality of instructions to the engine for driving the execution of the programs enabled by the engine, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the data device, the engine and the controller. The controller outputs one of the instructions to the engine for execution of one of the programs, while also executing an operation within itself, all within a single clock cycle.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: GEMICER, INC.Inventors: Dan Tomescu, Gheorghe Stefan
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Publication number: 20040123071Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: GEMICER, INC.Inventors: Gheorghe Stefan, Dan Tomescu