Abstract: A titanium dioxide micro-nanocontainers, corrosion-resistant waterborne epoxy coatings and preparation method thereof, including preparation steps as follows: TiO2 micro-nano spheres are synthesized by applying hydrothermal method; a polyaniline layer doped with molybdate ions is deposited on the surface of TiO2 micro-nano spheres by adopting the method of in-situ chemical polymerization, TiO2/PANI-MoO42? micro-nano-spheres are obtained, then, polydopamine is encapsulated on the surface of TiO2/PANI-MoO42? micro-nano spheres to obtain titanium dioxide micro-nanocontainers; next, antirust filler, defoamer, dispersant and thickener are added into waterborne epoxy emulsion, then titanium dioxide micro-nanocontainers are added in the waterborne epoxy emulsion for dispersing and grinding, filtering and encapsulating to obtain component A; the waterborne epoxy curing agent and deionized water are mixed in proportion to obtain component B; component A is stirred, then it is mixed with the component B in proportion,

Abstract: A program compilation method and apparatus operate by: obtaining a first expression and a second expression of a program, where the first expression and the second expression generate a dependency relationship based on a first variable, and operation types of the first variable in the first expression and the second expression are different, and updating an operation type of the first variable; so that the first variable has no differential result or a result is zero after encountering a differential operation; separately processing the first expression and the second expression according to the updated operation type of the first variable, to obtain a corresponding derivative function expression; and; combining, based on a chain rule, derivative function expressions respectively corresponding to the first expression and the second expression, to obtain a compilation result of the program.

Abstract: A fully-automatic aluminum thermal-spraying corrosion prevention production line based on robots and visual recognition is provided. The production line comprises an automatic feeding system comprising feeding carrying and conveying mechanisms; a laser derusting system comprising a derusting robot, a laser cleaning nozzle and derusting conveying mechanisms; an aluminum thermal-spraying system comprising an aluminum spraying robot and an aluminum thermal-spraying gun; an automatic rolling system comprising a rolling pedestal, a first rolling wheel, a second rolling wheel and a rolling drive mechanism; a laser cutting system; and a discharging and stacking system.

Abstract: An MOFs composite electrode material for supercapacitors includes: a Ni-BSC matrix, and a PEDOT coating layer coated on the Ni-BTC matrix, wherein a molar ratio of EDOT to Ni-BTC is 1:(1-4) based on a molar amount of EDOT monomer. A method for preparing the MOFs composite electrode material includes steps of: using nickel nitrate hexahydrate and benzenetricarboxylic acid as raw materials to synthesize Ni-BTC by a hydrothermal method; and using a liquid phase method to grow PEDOT on a surface of the Ni-BTC. An MOFs composite electrode slurry and a working electrode for the supercapacitors including the above MOFs composite electrode material or a MOFs composite electrode material prepared by the above method are also provided. The MOFs composite electrode material provided by the present invention combines advantages of Ni-BTC and PEDOT.

Abstract: Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

Abstract: A multi-dimensional mesh architecture is proposed to support transmitting data packets from one source to a plurality of destinations in multicasting or broadcasting modes. Each data packet to be transmitted to the destinations carries a destination mask, wherein each bit in the destination mask represents a corresponding destination processing block in the mesh architecture the data packet is sent to. The data packet traverses through the mesh architecture based on a routing scheme, wherein the data packet first traverses in a first direction across a first set of processing blocks and then traverses in a second direction across a second set of processing blocks to the first destination. During the process, the data packet is only replicated when it reaches a splitting processing block where the paths to different destinations diverge. The original and the replicated data packets are then routed in different directions until they reach their respective destinations.

Abstract: Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

Abstract: An MOFs composite electrode material for supercapacitors includes: a Ni-BSC matrix, and a PEDOT coating layer coated on the Ni-BTC matrix, wherein a molar ratio of EDOT to Ni-BTC is 1:(1-4) based on a molar amount of EDOT monomer. A method for preparing the MOFs composite electrode material includes steps of: using nickel nitrate hexahydrate and benzenetricarboxylic acid as raw materials to synthesize Ni-BTC by a hydrothermal method; and using a liquid phase method to grow PEDOT on a surface of the Ni-BTC. An MOFs composite electrode slurry and a working electrode for the supercapacitors including the above MOFs composite electrode material or a MOFs composite electrode material prepared by the above method are also provided. The MOFs composite electrode material provided by the present invention combines advantages of Ni-BTC and PEDOT.

Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Abstract: A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.

Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Abstract: A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

Abstract: A method of processing packets includes receiving packets and assigning the packets to different pages, where each page represents a fixed amount of memory. The different pages are distributed to different pools, where each pool has a unique mapping to banks, and where each bank is a set of memory resources. The different pages from the different pools are assigned to different banks in accordance with the unique mapping.

Abstract: A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether to invert a first group of data bit signals and performing error checking and correction on the first group of data bit signals in parallel with the inversion determination.

Abstract: Methods and systems for processing a single sub-channel that includes two or more combined channels. Using intermediate frequency sub-sampling, two or more channels from a broad band signal are combined into a single sub-channel for further analog and digital processing. Each of the two or more channels is down converted to an intermediate frequency, filtered to remove certain undesired channels, and combined such that the two or more channels are adjacent to each other. A digital representation of the sub-channel is produced from the combined intermediate frequency channels. Each channel within the digital representation is down converted to baseband, and the in-phase and quadrature components are separated from each other. Compared to one direct down conversion technique, intermediate frequency sub-sampling as described in the application may reduce the number of analog to digital converters and control amplifiers used in analog processing by a factor of four.