Patents by Inventor Dan Turpuseema

Dan Turpuseema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and structure for forming contact pads on a printed circuit board using zero under cut technology
    Patent number: 9468108
    Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: October 11, 2016
    Assignee: Abacus Finance Group LLC
    Inventors: Dan Turpuseema, James V. Russell
  • Method and structure for forming contact pads on a printed circuit board using zero under cut technology
    Publication number: 20140069704
    Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.
    Type: Application
    Filed: July 25, 2013
    Publication date: March 13, 2014
    Applicant: R&D Circuits, Inc.
    Inventors: Dan Turpuseema, James V. Russell