Patents by Inventor Dan UMEDA

Dan UMEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190005155
    Abstract: A sever communicates with a terminal device and a data management device. The terminal device displays a visualization screen. The data management device generates aggregate data in which original data is aggregated. The server includes one or more circuitry configured to receive customization information indicating setting related to the visualization screen from the terminal device, cause a storage to store therein screen configuration information indicating a screen configuration of the visualization screen based on the customization information, create a request for generating the aggregate data based on the customization information and the screen configuration information, and transmit the request to the data management device.
    Type: Application
    Filed: February 16, 2018
    Publication date: January 3, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Xinxiao Li, Hidenori Matsuzaki, Dan Umeda
  • Publication number: 20180275941
    Abstract: According to an embodiment, a display control system includes a memory and one or more hardware processors configured to function as a determining unit, a generating unit, and a display control unit. The determining unit is configured to determine whether to aggregate individual data into aggregated data using a narrowing condition for the individual data. The generating unit is configured to generate the aggregated data from the individual data in a case where the individual data is aggregated into the aggregated data. The display control unit is configured to display the individual data in a case where the individual data is not aggregated into the aggregated data and display the aggregated data in a case where the individual data is aggregated into the aggregated data.
    Type: Application
    Filed: August 23, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Dan UMEDA, Hidenori MATSUZAKI, Akira KURODA, Xinxiao LI
  • Publication number: 20180276310
    Abstract: According to an embodiment, an information processing system includes one or more memories and one or more processors coupled to the memories. The one or more processors are configured to receive a start time and an end time, and use time series information including data for which time information is associated with numerical information and index information including data for which a time range of the time information is associated with tabulation information tabulated for each time range of the time information, refer to the tabulation information associated with time information between the time range including the start time and the time range including the end time, and extract the tabulation information corresponding to a period between the start time and the end time.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hidenori MATSUZAKI, Akira KURODA, Xinxiao LI, Dan UMEDA
  • Publication number: 20180181380
    Abstract: There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatus 100 includes a fusion step (FIG. 2/STEP026) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.
    Type: Application
    Filed: December 28, 2017
    Publication date: June 28, 2018
    Inventors: Hironori Kasahara, Keiji Kimura, Dan Umeda, Hiroki Mikami
  • Publication number: 20180175688
    Abstract: Provided is a rotating machine capable of obtaining a uniform temperature distribution by improving a cooling air flow to a heat generation portion. The rotating machine has a salient pole rotor (11) and a stator (12). The salient pole rotor (11) has a rotation shaft (15), a disk-shaped spoke (22), a cylindrical rib (23), and a plurality of salient poles (25) arranged in a radial shape on an outer circumferential surface of the rib (23), each of the salient poles (25) being formed along an axial direction of the rotation shaft (15). The disk-shaped spoke (22) is provided to an anti-feeding side end of the cooling air of the salient pole rotor (11). The cylindrical rib (23) is provided with through-holes (231) extending from an inner space of the cylindrical rib (23) through gaps between a plurality of salient poles (25).
    Type: Application
    Filed: June 20, 2016
    Publication date: June 21, 2018
    Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Takayuki MIHARA, Dan UMEDA
  • Patent number: 9934012
    Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 3, 2018
    Assignees: DENSO CORPORATION, WASEDA UNIVERSITY
    Inventors: Kazushi Nobuta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mikami, Dan Umeda
  • Patent number: 9760355
    Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 12, 2017
    Assignees: DENSO CORPORATION, WASEDA UNIVERSITY
    Inventors: Hiroshi Mori, Mitsuhiro Tani, Hironori Kasahara, Keiji Kimura, Dan Umeda, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi
  • Publication number: 20160291949
    Abstract: A parallelization compiling method includes analyzing a sequential program prepared for a single-core processor; dividing the sequential program into a plurality of processes based on an analysis result; and generating a parallelized program, which is subjected to a parallelized execution by a multi-core processor, from the plurality of processes. The generating of the parallelized program includes compiling the plurality of processes under an execution order restriction defined based on a predetermined parameter.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Inventors: Kenichi MINEDA, Noriyuki SUZUKI, Hironori KASAHARA, Keiji KIMURA, Hiroki MIKAMI, Dan UMEDA
  • Publication number: 20160291950
    Abstract: A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Inventors: Yoshihiro YATOU, Noriyuki SUZUKI, Kenichi MINEDA, Hironori KASAHARA, Keiji KIMURA, Hiroki MIKAMI, Dan UMEDA
  • Publication number: 20160291948
    Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Inventors: Kazushi NOBUTA, Noriyuki SUZUKI, Hironori KASAHARA, Keiji KIMURA, Hiroki MIKAMI, Dan UMEDA
  • Publication number: 20150363230
    Abstract: A method of extracting parallelism of an original program by a computer includes: a process of determining whether or not a plurality of macro tasks to be executed after a condition of one conditional branch included in the original program is satisfied are executable in parallel; and a process of copying the conditional branch regarding which the macro tasks are determined to be executable in parallel, to generate a plurality of conditional branches.
    Type: Application
    Filed: January 15, 2014
    Publication date: December 17, 2015
    Applicant: Waseda University
    Inventors: Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada
  • Publication number: 20140372995
    Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Hiroshi MORI, Mitsuhiro TANI, Hironori KASAHARA, Keiji KIMURA, Dan UMEDA, Akihiro HAYASHI, Hiroki MIKAMI, Yohei KANEHAGI