Abstract: Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.

Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Abstract: An electronic component for failure detection and analysis of bus activity comprises configuration circuitry, a buffer, and read circuitry. The configuration circuitry, the buffer, the read circuitry and the bus being tracked are on the same die. The configuration circuitry identifies one or more modes, one or more triggers, and one or more responses associated with the triggers. The buffer stores transactions on a bus according to the configuration circuitry. The read circuitry reads data from the buffer. A method of tracking bus activity comprises configuring a bus activity tracking component; monitoring an interface for a trigger event; and performing associated responses upon the occurrence of the trigger event.

Abstract: A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.

Abstract: A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.

Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Abstract: An apparatus and method are disclosed for providing concurrent access to first storage area and a second storage area. According to one embodiment, a device includes the first storage area. The device and the second storage area are both coupled to a first bus and are coupled together by a dedicated second bus. According to one embodiment, a snoop operation on the first storage area be preferred concurrently with a snoop operation on the second storage area.

Abstract: A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.