Patents by Inventor Dan Y. Chen

Dan Y. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6800985
    Abstract: The present invention relates to a process for mounting and heatsinking a piezoelectric transformer (PT). The method provides a method to mount a PT, while allowing heat generated in the device to be conducted away to the mounting surface. The method can be used in piezoelectric transformer based ballasts and power supplies such that high power levels may be achieved due to minimizing thermal constraints on the devices.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: October 5, 2004
    Inventors: Eric M. Baker, Weixing Huang, Dan Y. Chen, Fred C. Lee
  • Publication number: 20030020372
    Abstract: The present invention relates to a process for mounting and heatsinking a piezoelectric transformer (PT). The method provides a method to mount a PT, while allowing heat generated in the device to be conducted away to the mounting surface. The method can be used in piezoelectric transformer based ballasts and power supplies such that high power levels may be achieved due to minimizing thermal constraints on the devices.
    Type: Application
    Filed: April 22, 2002
    Publication date: January 30, 2003
    Inventors: Eric M. Baker, Weixing Huang, Dan Y. Chen, Fred C. Lee
  • Patent number: 4851769
    Abstract: A non-destructive reverse-bias second breakdown tester for testing semiconductor devices such as transistors and thyristors that have a base-collector-emitter configuration. The tester basically comprises a socket for holding the device under test. A base drive provides a drive current to the base of the device under test. A collector supply provides a collector current to the device under test. A current diverter diverts current away from the device under test when the device under test experiences reverse-bias second breakdown. The diverter includes first, second and third switches arranged in series. A diode diverter is connected to the current supply and the third switch. A detector produces a first signal at the onset of reverse-bias second breakdown in the device under test. In response to the first signal, the first, second and third switches are activated in seriatim.
    Type: Grant
    Filed: April 11, 1988
    Date of Patent: July 25, 1989
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Grant Carpenter, Fred C. Lee, Dan Y. Chen
  • Patent number: 4547686
    Abstract: The voltage rating of a bipolar transistor may be greatly extended while at the same time reducing its switching time by operating it in conjunction with FETs in a hybrid circuit. One FET is used to drive the bipolar transistor while the other FET is connected in series with the transistor and an inductive load. Both FETs are turned on or off by a single drive signal of load power, the second FET upon ceasing conduction, rendering one power electrode of the bipolar transistor open. Means provided to dissipate currents which flow after the bipolar transistor is rendered nonconducting.
    Type: Grant
    Filed: September 30, 1983
    Date of Patent: October 15, 1985
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Dan Y. Chen