Patents by Inventor Dan Zupcau

Dan Zupcau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8861158
    Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: October 14, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Dan Zupcau
  • Patent number: 8576524
    Abstract: An electrostatic discharge (ESD) detector is coupled to the input voltage, and includes a voltage modulated input capacitance Cj configured to decrease as the input voltage increases. An output pulse generator is coupled to an output of the detector, and configured to amplify the output of the detector. An ESD protection switch is coupled to turn on upon application of an output pulse from the output pulse generator.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 5, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Dan Zupcau, Leo Luquette
  • Publication number: 20110261489
    Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 27, 2011
    Applicant: Cypress Semiconductor Corporation
    Inventor: Dan Zupcau
  • Patent number: 7660086
    Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 9, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Thurman John Rodgers, Babak Taheri, Dan Zupcau
  • Publication number: 20070285854
    Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.
    Type: Application
    Filed: June 8, 2006
    Publication date: December 13, 2007
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventors: Thurman John Rodgers, Babak Taheri, Dan Zupcau
  • Patent number: 7184253
    Abstract: A circuit (100) can include a first section (102) that can provide a designated function within an integrated circuit device that can be altered due to current injection at a node (106). A mirror section (104) can mirror the effects of current injection on one or more devices within first section (102) and generate an output indication INJ_EFF representing such effects. In one very particular arrangement, detection of an injected current can be used to prevent false triggering of a switched electrostatic discharge (ESD) current path.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: February 27, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Marc Hartranft, Eric Mann, Dan Zupcau