Abstract: Compact and high speed logic circuits that utilize CMOS technology to perform the Boolean operations A.multidot.B and A+B. The presently disclosed logic circuits are comprised of a field effect transistor and first and second logic performing diodes which are uniquely interconnected with one another so as to reduce the number of circuit components and to increase the operating speed relative to conventional logic circuits.

Abstract: An improved, compact high-speed inverting power driver fabricated from field effect transistors and capable of driving a relatively heavy load to full -V.sub.DD power supply voltage. The power driver includes a pair of positive feedback circuits having respective bootstrap capacitors arranged therein. The bootstrap capacitors are initially precharged, and the feedback paths act to substantially boost the voltage applied to operate a driver transistor so as to enable the load to be ultimately driven to a full -V.sub.DD voltage level via the conduction path of the driver transistor.

Abstract: A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer stage which, in the preferred embodiment, is adapted to be interfaced with a random access memory array comprised of a plurality of discrete, non-symmetrical memory cells. The integrated circuit is designed so that the space consumed thereby and the corresponding cost of production can be minimized.

Abstract: An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, decreasing the overall cell area and consequently the cost, the cell is made highly non-symmetrical in design. As an example, selected ones of the semiconductor transistors may have reduced channel widths with respect to one another.

Abstract: Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

Abstract: A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification stage, where such is required.