Abstract: Methods of controlling the illumination source (18) of an SLM-based display system (10). It is assumed that the system (10) displays pixel data formatted into a bit-plane format so that all bits of the same bit-weight can be displayed simultaneously. To provide greyscale, the amplitude of the source (18) may be modulated so that bit-planes having greater bit-weights are displayed with more intense illumination than bit-planes having smaller bit-weights (FIGS. 2 and 3). To avoid visual artifacts, the duty cycle of the bit-plane display times may be shortened relative to the frame period. (FIG. 4A). The latter method can be accompanied by a shortening of the duty time of the illumination on SLM (15). (FIG. 4B). The short duty cycle method may be used together with illumination amplitude modulation, or it may be used with the PWM method of providing greyscale.

Abstract: This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is a band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.

Abstract: This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.

Abstract: A thermal imaging system (10) contains a focal plane array (14) including a plurality of thermal sensors (50) mounted on a substrate (52). The focal plane array (14) generates both a reference signal which represents the temperature of the substrate (52) and a biased signal corresponding to the total radiance emitted by a scene (11). Electronics (16) process the reference signal and the biased signal to obtain an unbiased signal representing radiance differences emitted by objects in the scene (11). A thermoelectric cooler/heater (38) may be provided to optimally adjust the temperature of the substrate (52) to improve overall image quality. Each thermal sensor (50) contains an electrode (66 and 68) that electrically couples the thermal sensor (50) to the substrate (52) and also allows the thermal sensor (50) to deflect, contact, and thermally shunt with the substrate (52).

Abstract: A circuit and method of detecting infrared radiations with a focal plane array circuit member comprising storing a charge in a storage device indicative of the intensity of received infrared radiations, periodically transferring the stored charge and then resetting the storage device, storing the transferred charge, providing an output terminal and providing a low pass filter coupled between the output terminal and the storage means.

Abstract: A monolithic infrared detector readout circuit for a capacitive detection element wherein a high gain preamplifier is biased by a large amplifier feedback resistance, on the order of 10.sup.12 ohms. The output of the preamplifier is bandlimited by a low pass single-pole filter having a high value resistor on the order of 10.sup.9 ohms and then is buffered prior to being multiplexed by row address signals. The output from the multiplexer switch is then applied to the column line for output to a video circuit or the like.

Abstract: A signal peaking device for a single line video input has a transversal filter with a plurality of sample and hold (S & H) circuits, a corresponding plurality of line drivers and output switches. The output switches are connected to a plurality of weighting circuits and a summer that sums the weighted output of the output switches. A free running digital shift register generates the sample pulse that operates the sample and hold circuits.

Abstract: A monolithic delta frame circuit comprises a high speed line address circuit, demultiplexer, line shift register, plurality of buffer amplifiers, an array of difference frame elements, reset circuit means, plurality of sample and hold circuits, multiplexer, and a high speed line address circuit. The high speed line address circuit clocks a single line video input at a fast rate into the demultiplexer for demultiplexing into the line shift register, the line shift register shifts the single line signals and noise into the elements of the array of difference frame elements. As the data from the previous frame which consists of noise or noise minus signal is still present in the difference elements only the signal or delta signal portion feeds through a reset circuit at a slower rate to the multiplexer. The reset circuit introduces offset noises into the signal which is substantially reduced by feedback through the reset circuit.

Abstract: An improved visible and near infrared imaging system, in a first embodiment, has an optical system, chopper, improved detector, improved first and second delta frames, display, and timing and control circuits. The detector is a parallel amplification type detector with the sense lines each including a total subtraction chain. Each parallel amplifier chain is split so that two branches exist, each containing sample and hold circuits and one with a gain of -C.sub.s /(C.sub.d +C.sub.s) times the other. The outputs of the amplifier chains are multiplexed to the first delta frame for storage by frame for summation with the outputs of the next frame for substantially reducing the reset noise. The summed output signals are multiplexed at a 2x rate into the second delta frame for removal of the pattern noise and multiplexed out at a 1x rate for display.

Abstract: A visible light and near infrared imaging device is disclosed. The imaging device comprises X-Y addressing means, an array of opto-electronic semiconductor elements or cells, a multiplexer, a precharge switch, and an amplifier. The X-Y addressing means selectively addresses each cell of the array of opto-electronic semiconductor cells and corresponding multiplexer switch for connecting a reference voltage to each cell to charge each element to the reference voltage, then to isolate each element and vary its voltage in proportion to the intensity of the impinging light, and finally to read out selectively the voltage of each element to the amplifier for amplifying the electrical signals representative of the light intensity to a working level for processing into video signals.

Abstract: A delta frame circuit is disclosed. The delta frame circuit is connected to the video output of, for example, an imaging system for the purpose of producing a moving target indication radar or, for example, a chopped imaging system for the purpose of removing fixed pattern or undesirable offset voltages. The delta frame circuit comprises a plurality of capacitors having top plates connected to the video output and lower plates connected to the drains of a first plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a Y address circuit and drains of a second plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a X address circuit and to the drains of a third plurality of field effect transistors whose gates and sources are connected, respectively, to the Y address circuit, and junction of a precharge reference voltage and output amplifier.