Patents by Inventor Dana How
Dana How has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9922157Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.Type: GrantFiled: July 17, 2015Date of Patent: March 20, 2018Assignee: Altera CorporationInventors: Carl Ebeling, Herman Henry Schmit, Dana How, Mahesh A. Iyer, Saurabh Adya
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Publication number: 20180069533Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Inventors: Dana How, Herman Henry Schmit
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Patent number: 9843332Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.Type: GrantFiled: April 25, 2017Date of Patent: December 12, 2017Assignee: Altera CorporationInventors: Ramanand Venkata, Dana How, Christopher Lane
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Patent number: 9806696Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.Type: GrantFiled: December 22, 2015Date of Patent: October 31, 2017Assignee: ALTERA CORPORATIONInventors: Dana How, Herman Henry Schmit
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Patent number: 9703526Abstract: An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.Type: GrantFiled: March 12, 2015Date of Patent: July 11, 2017Assignee: Altera CorporationInventor: Dana How
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Patent number: 9698784Abstract: Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.Type: GrantFiled: July 1, 2016Date of Patent: July 4, 2017Assignee: Altera CorporationInventor: Dana How
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Patent number: 9685957Abstract: An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses.Type: GrantFiled: April 9, 2014Date of Patent: June 20, 2017Assignee: Altera CorporationInventor: Dana How
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Patent number: 9660630Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.Type: GrantFiled: October 17, 2016Date of Patent: May 23, 2017Assignee: Altera CorporationInventors: Ramanand Venkata, Dana How, Christopher Lane
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Patent number: 9606573Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.Type: GrantFiled: June 26, 2015Date of Patent: March 28, 2017Assignee: Altera CorporationInventors: Carl Ebeling, Dana How, Herman Henry Schmit, Vadim Gutnik, Ramanand Venkata
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Patent number: 9602587Abstract: Systems and methods are provided herein for implementing a Network-on-Chip (NoC) in a System-on-Chip (SoC) device. In some embodiments, an NoC may include a first node that transmits data to a second node, where data may be transmitted via either a first plane or a second plane. The first plane may utilize first logic at each of an output port of the first node, an input port of the second node, and at intermediary ports when transmitting the data to the second node. The second plane may utilize first logic at the output port of the first node and at the input port of the second node when transmitting the data to the second node, and may utilize second logic that is different from the first logic at the intermediary ports when transmitting the data to the second node.Type: GrantFiled: June 26, 2014Date of Patent: March 21, 2017Assignee: Altera CorporationInventor: Dana How
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Patent number: 9588176Abstract: An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.Type: GrantFiled: January 30, 2015Date of Patent: March 7, 2017Assignee: Altera CorporationInventors: Michael Hutton, Sean Atsatt, James Ball, Dana How, Jeffrey Chromczak, Eng Ling Ho
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Publication number: 20170041249Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: Michael David Hutton, Herman Henry Schmit, Dana How
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Patent number: 9553762Abstract: Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.Type: GrantFiled: June 26, 2014Date of Patent: January 24, 2017Assignee: Altera CorporationInventors: Dana How, Herman Henry Schmit, Sean R. Atsatt
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Publication number: 20160363626Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
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Publication number: 20160358638Abstract: An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2× functional blocks, and data spreading circuitry at the output of the 2× functional blocks.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Martin Langhammer, Dana How
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Patent number: 9503057Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.Type: GrantFiled: December 20, 2013Date of Patent: November 22, 2016Assignee: Altera CorporationInventors: Ramanand Venkata, Dana How, Christopher Lane
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Patent number: 9501092Abstract: Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first clock signal having first clock edges, a second register in a second stage that receives a first signal from the first stage, and having a second clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.Type: GrantFiled: December 18, 2015Date of Patent: November 22, 2016Assignee: Altera CorporationInventors: Dana How, Carl Ebeling, Audrey Catherine Kertesz
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Patent number: 9479456Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.Type: GrantFiled: October 29, 2013Date of Patent: October 25, 2016Assignee: Altera CorporationInventors: Michael David Hutton, Herman Henry Schmit, Dana How
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Patent number: 9473112Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.Type: GrantFiled: December 20, 2013Date of Patent: October 18, 2016Assignee: Altera CorporationInventors: Ramanand Venkata, Dana How, Christopher Lane
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Publication number: 20160268005Abstract: An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.Type: ApplicationFiled: March 12, 2015Publication date: September 15, 2016Inventor: Dana How