Abstract: A method may include receiving, by a transducer driving system, a first signal for driving an amplifier that drives an electromagnetic load and receiving, by the transducer driving system, a second signal driven by the amplifier in order to control a feedback loop of the transducer driving system. The method may also include detecting unexpected spectral content in the second signal, declaring an indicator event based on the detected unexpected spectral content, determining whether the indicator event occurs in an undesired pattern, and in response to the indicator event occurring in the undesired pattern, modifying a behavior of the transducer driving system.

Abstract: A method for generating a signal for a device process may include retrieving a reduced-memory template signal centered on a chosen subharmonic of a reconstruction sample rate, upsampling the reduced-memory template signal to generate the signal for the device process at a desired data rate, and communicating the signal to a transducer for playback by the transducer.

Abstract: Circuitry for acoustic crosstalk cancellation between first and second acoustic signals, the circuitry comprising: crosstalk cancellation circuitry configured to: receive a first audio signal and, based on the received first audio signal, generate a first crosstalk cancellation signal; receive a second audio signal and, based on the received second audio signal, generate a second crosstalk cancellation signal; combine the first crosstalk cancellation signal with a signal indicative of the second audio signal to generate a first crosstalk cancellation circuitry output signal; and combine the second crosstalk cancellation signal with a signal indicative of the first audio signal to generate a second crosstalk cancellation circuitry output signal; and output stage circuitry configured to: receive the first crosstalk cancellation circuitry output signal and, based on the received first crosstalk cancellation circuitry, generate a first drive signal for driving a first speaker to generate the first acoustic signal

Abstract: A system may include a first input for receiving a first signal for driving an amplifier that drives a load, a second input for receiving a second signal driven by the amplifier, and an instability detector for detecting instability of a feedback loop for controlling the first signal based on comparison of the first signal and the second signal.

Abstract: A method may include receiving, by a transducer driving system, a first signal for driving an amplifier that drives an electromagnetic load and receiving, by the transducer driving system, a second signal driven by the amplifier in order to control a feedback loop of the transducer driving system. The method may also include detecting unexpected spectral content in the second signal, declaring an indicator event based on the detected unexpected spectral content, determining whether the indicator event occurs in an undesired pattern, and in response to the indicator event occurring in the undesired pattern, modifying a behavior of the transducer driving system.

Abstract: A system may include a first input for receiving a first signal for driving an amplifier that drives a load, a second input for receiving a second signal driven by the amplifier, and an instability detector for detecting instability of a feedback loop for controlling the first signal based on comparison of the first signal and the second signal.

Abstract: A radio receiver includes a processing unit that may generate a respective phase value corresponding to each of a plurality of digital samples of a received complex frequency modulation (FM) signal. The receiver also includes an impulse unit that may detect whether a linear combination of a phase value of a current sample and a phase value of one or more previous samples will produce an impulse at an output of an FM demodulator. If the impulse unit detects that an impulse will be produced at the output, the impulse unit may replace the output of the FM discriminator with a predetermined value.

Abstract: Low-IF terrestrial data receivers and related communication systems and methods are disclosed that provide efficient solutions for reception of data services in FM broadcast channels. In particular, systems and methods are provided for data service information modulated on a 67.65 kHz sub-carrier, for example, using QPSK modulation. Intermediate data service information is output by the data receiver, and this intermediate data service information takes the form of demodulated digital I/Q signals provided through a digital interface of the data receiver. As such, partial digital signal processing is provided by the data receiver and the remaining digital processing is provided by a host processor.

Abstract: A frequency modulation (FM) radio receiver includes a processing unit that may generate a magnitude value corresponding to a signal strength of each of a plurality of digital samples of a received FM signal. The receiver also includes a noise estimation unit that may filter the magnitude values using a high pass filter and may generate a noise value representative of a noise portion of the received FM signal based upon the filtered magnitude values.

Abstract: A Code Division Multiple Access (CDMA) post-correlation processing system (12) for delay locked loop processing reduces the control data rate into a delay locked loop (DLL) processor and the number of required interpolation operations by executing a portion of the interpolation operations at a symbol data rate rather than at a chiprate. Specifically, an interpolator (16) generates time shifted chip samples based on input CDMA chip samples. First and second correlators (22, 24) extract ontime control and data symbol samples, respectively, from ontime input CDMA chip samples. A third correlator (26) extracts first non-ontime control symbol samples from non-ontime CDMA chip samples. The first non-ontime control symbol samples are then input with the ontime control symbol samples to a post-correlation interpolator (28) operating at a symbol rate to generate second non-ontime symbol samples necessary for Delay Locked Loop (DLL) processing.

Abstract: A CDMA post-correlation processing system (12) for delay locked loop processing reduces the control data rate into a delay locked loop processor and the number of required interpolation operations by executing a portion of the interpolation operations at a symbol data rate rather than at a chiprate. Specifically, an interpolator (16) generates time shifted chip samples based on input CDMA chip samples. First and second correlators (22, 24) extract ontime control and data symbol samples, respectively, from ontime input CDMA chip samples. A third correlator (26) extracts first non-ontime control symbol samples from non-ontime CDMA chip samples. The first non-ontime control symbol samples are then input with the ontime control symbol samples to a post-correlation interpolator (28) operating at a symbol rate to generate second non-ontime symbol samples necessary for DLL processing.

Abstract: In a decoding system having a first constituent decoder and a second constituent decoder, a sequence of inputs that includes a system input, a first parity input, and a second parity input, is decoded. The first constituent decoder receives a feedback input and the first parity input, and based on these inputs, the first constituent decoder produces a first constituent decoder output. The output of the first constituent decoder is modified to obtain a first combined feedback and system input, thereby including a statistical dependency. The second constituent decoder receives this combined input and the second parity input and based on these inputs, produces a second constituent decoder output. The second constituent decoder output is processed to produce decoded bits. Embodiments further include modifying the output of the second constituent decoder and providing the modified output as the feedback to the first constituent decoder.

Abstract: The present invention includes methods relating generally to communication systems. In decoding a sequence of symbols output by an encoder having a first constituent encoder and a second constituent encoder, where the output of these encoders correspond to unterminated trellises, a forward calculation is performed along each trellis to compute a forward state metric value for a first node of each trellis. Prior to performing a backward calculation along each trellis, a backward state metric value of a second node of each trellis is initialized to the forward state metric values of the corresponding first nodes of each trellis. Using these forward and backward state metric values, the sequence of symbols is decoded. Other embodiments include decoding terminated trellises in a similar manner, or dividing each trellis into smaller windows and processing the series of windows.