Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a queue depth for the request queue, determining a target interval based on the queue depth and a target queue depth, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling an interval between requests. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, and responsive to the time interval being less than a target interval, delaying acting on the second request until after the target interval.

Abstract: Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a non-volatile memory (NVM) and a controller circuit. The NVM stores a plurality of data sets encrypted by at least one encryption key. The controller circuit performs a storage compute appliance process by locally decrypting the plurality of data sets in a local memory of the data storage device, generating summary results data from the decrypted data sets, and transferring the summary results data across the host interface to an authorized user without a corresponding transfer of any portion of the decrypted data sets across the host interface.

Abstract: Methods, apparatuses, and computer-readable media for providing extremely rapid preconditioning of an SSD. Upon receiving a precondition command from a host operably connected to the SSD to precondition a range of LBAs of the storage media, a plurality of physical units of the storage media to be preconditioned are determined based on the range of LBAs. A workload pattern is determined from the precondition command, and upon determining that the workload pattern indicates a random pattern, a valid page count for each of the plurality of physical units is computed based on a random distribution. Forward mapping table entries of a forward mapping table associated with the storage media corresponding to the range of LBAs is then populated with random physical addresses from the plurality of physical units based at least on the computed valid page count for each of the plurality of physical units.

Abstract: Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a controller circuit and a non-volatile memory (NVM) with an overall data storage capacity. A processor authenticates each of a plurality of authorized users of the NVM via data exchanges between a host device and the processor without reference to an external authentication authority device. Upon authentication, each authorized user is allocated a separate portion of the overall data storage capacity of the NVM using an allocation model. The size of at least one of the separate portions is subsequently adjusted based on an access history of the NVM. The storage device may be a key-value storage device so that a separate set of key values is provided to each authorized user to identify data blocks stored to and retrieved from the NVM.

Abstract: Technologies are described herein for implementing a space-efficient internal energy storage apparatus in a data storage device or other electronic device have a metallic or otherwise electrically-conductive housing or case structure. A first carbon layer is applied to an inner surface of the metallic housing, and a dielectric spacer is applied upon the first carbon layer. Next, a conductive layer having a second carbon layer is applied over the dielectric spacer, and the metallic housing and the conductive layer is electrically connected to a circuitry of the electronic device.

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

Abstract: Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a non-volatile memory (NVM) and a controller circuit. The NVM stores a plurality of data sets encrypted by at least one encryption key. The controller circuit performs a storage compute appliance process by locally decrypting the plurality of data sets in a local memory of the data storage device, generating summary results data from the decrypted data sets, and transferring the summary results data across the host interface to an authorized user without a corresponding transfer of any portion of the decrypted data sets across the host interface.

Abstract: Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a controller circuit and a non-volatile memory (NVM) with an overall data storage capacity. A processor authenticates each of a plurality of authorized users of the NVM via data exchanges between a host device and the processor without reference to an external authentication authority device. Upon authentication, each authorized user is allocated a separate portion of the overall data storage capacity of the NVM using an allocation model. The size of at least one of the separate portions is subsequently adjusted based on an access history of the NVM. The storage device may be a key-value storage device so that a separate set of key values is provided to each authorized user to identify data blocks stored to and retrieved from the NVM.

Abstract: Technologies are described herein for implementing a space-efficient internal energy storage apparatus in a data storage device or other electronic device have a metallic or otherwise electrically-conductive housing or case structure. A first carbon layer is applied to an inner surface of the metallic housing, and a dielectric spacer is applied upon the first carbon layer. Next, a conductive layer having a second carbon layer is applied over the dielectric spacer, and the metallic housing and the conductive layer is electrically connected to a circuitry of the electronic device.

Abstract: Technologies are described herein for implementing a space-efficient internal energy storage apparatus in a data storage device or other electronic device have a metallic or otherwise electrically-conductive housing or case structure. The energy storage apparatus comprises an interior surface of the metallic housing, a conductive layer disposed parallel to the interior surface of the metallic housing, and a separator disposed between the interior surface and the conductive layer. The metallic housing is configured to act as a first electrode of the energy storage apparatus and the conductive layer is configured to act as an opposing electrode to the first electrode.

Abstract: Systems and methods presented herein provide for data storage for a plurality of host systems. In one embodiment, a storage system comprises a storage unit, and a controller. The controller is operable to process a write I/O request from a first of the host systems, to determine an identity of the first host system from the write I/O request, to encrypt data of the write I/O request based on the identity of the first host system, to locate a storage space allocated to the first host system in the storage unit, to determine that a size of the data of the write I/O request requires more storage space than currently allocated to the first host system, to increase the storage space allocated to the first host system by the size of the data of the write I/O request, and to write the encrypted data to the storage unit.

Abstract: Technologies are described herein for implementing a space-efficient internal energy storage apparatus in a data storage device or other electronic device have a metallic or otherwise electrically-conductive housing or case structure. The energy storage apparatus comprises an interior surface of the metallic housing, a conductive layer disposed parallel to the interior surface of the metallic housing, and a separator disposed between the interior surface and the conductive layer. The metallic housing is configured to act as a first electrode of the energy storage apparatus and the conductive layer is configured to act as an opposing electrode to the first electrode.