Abstract: Data partitioned onto two or more storage devices is presented to a user as if the data resided on a single storage area. Data is divided between the storage areas based on policies. Data on the primary storage can utilize frequent back up or other storage management to ensure the accuracy of the data. The data on the secondary storage can employ other data management than the data management for the primary storage. The subdirectory structure is replicated in each area so a data file can be located in either physical area. This allows data files to migrate between the storage areas based on policy.

Abstract: A checksum generator includes at least one adding circuit for processing a segment of a given message. Associated with the adding circuit is a register for temporarily holding the partial sum that is being calculated by the adding circuit. The register is configured to hold a partial sum that is larger than the message segments being added by the adding circuit. The partial sums can thus expand into the register, eliminating the creation of a carry bit that must be added back in during each add cycle. After the last message segment has been processed, the adding circuit preferably adds the high order portion of the register to the low order portion and adds back any carry bit generated thereby to produce a checksum value that may be loaded into the given message.

Abstract: A method and apparatus for improving multi-processor performance where the various processors are competing for spinlock acquisition is described. If a spinlock testing processor fails to acquire the spinlock, it re-tries for access after a small wait interval has passed. If the spinlock is still locked, the testing processor retries with an additional increase in the wait interval. Subsequent re-tries progressively increases the wait interval until a maximum wait interval is reached. At this point, the wait interval is reset back to an initial small wait interval and the procedure is repeated until the processor gains access to the spinlock.

Abstract: A checksum generator includes at least one adding circuit for processing a segment of a given message. Associated with the adding circuit is a register for temporarily holding the partial sum that is being calculated by the adding circuit. The register is configured to hold a partial sum that is larger than the message segments being added by the adding circuit. The partial sums can thus expand into the register, eliminating the creation of a carry bit that must be added back in during each add cycle. After the last message segment has been processed, the adding circuit preferably adds the high order portion of the register to the low order portion and adds back any carry bit generated thereby to produce a checksum value that may be loaded into the given message.