Abstract: Adding a layer of abstraction to the generation of a runset for DRC rules, by defining a meta language hides from the user the language of a specific verification tool (also called “native language”). The meta language can be used directly by the user to express in a file (also called “meta runset”) the DRC rules to be used to create an input for the verification tool in the native language (also called simply “runset”). A runset generator uses DRC rules supplied by a user to generate a runset in a native language (that is identified by the user). The runset generator can use templates to generate a runset. Each template (also called “DRC template”) contains code (can be in source form or in object form) for implementation of a DRC rule or derived layer in the native language of a specific verification tool (such as HERCULES). Thus implementation of DRC rules is hidden from the novice user.

Abstract: A method automatically specifies a unique number of an error layer for each DRC rule in a runset. Therefore, all errors related to a given DRC rule are reported by a layout verification tool in the uniquely specified error layer. Furthermore, the method also automatically specifies a unique number of a filter layer that has the same extent as a quality assurance (QA) cell for testing the DRC rule. The filter layer is logically operated (e.g. ANDed) with the error layer to uniquely identify a failure related to the DRC rule (i.e. errors from all other QA cells are filtered out). The QA cells are generated automatically by use of a library of templates. During regression testing, the first time a DRC runset is run against a test design or QA cell library the results are manually verified and stored as “expected” results.

Abstract: A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

Abstract: A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).