Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

Abstract: Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.

Abstract: Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.

Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

Abstract: Embodiments of the present invention are directed to optical broadcast systems. The nodes of the system can be any combination of cores, caches, input/output devices, and memory, or any other information processing, transmitting, or storing device. The optical broadcast system includes an optical broadcast bus. Any node of the system in optical communication with the broadcast bus can broadcast information in optical signals to all other nodes in optical communication with the broadcast bus.

Abstract: Embodiments of the present invention are directed to optical broadcast systems (100,140,160,180). The nodes of the system can be any combination of cores, caches, input/output devices, and memory, or any other information processing, transmitting, or storing device. The optical broadcast system includes an optical broadcast bus (142,162,182). Any node of the system in optical communication with the broadcast bus can broadcast information in optical signals to all other nodes in optical communication with the broadcast bus.