Abstract: Equipment and method for the rapid and easy extraction of formed metal parts from forming dies while in a press and operating at elevated temperatures. The invention features the controlled supply of streams of air or other inert gas to the interface of the hot surface of the forming die and the formed panel to augment removal so that flaws from removal equipment are minimized for optimized production of high quality parts. High velocity air is discharged through nozzles onto the forming surfaces of hot forming dies to cool the forming die and the part that contract at different rates and pop the part from the surface.

Abstract: Equipment and method for the rapid and easy extraction of formed metal parts from forming dies while in a press and operating at elevated temperatures. The invention features the controlled supply of streams of air or other inert gas to the interface of the hot surface of the forming die and the formed panel to augment removal so that flaws from removal equipment are minimized for optimized production of high quality parts. High velocity air is discharged through nozzles onto the forming surfaces of hot forming dies to cool the forming die and the part that contract at different rates and pop the part from the surface.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: A memory subsystem couples to a single word bus in common with a central processing unit for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which specifies the row of chips to be accessed within a first one of the pair of memory units. The subsystem further includes control circuits, common timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom.