Patents by Inventor Dandan Li

Dandan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080136534
    Abstract: Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 12, 2008
    Inventor: Dandan Li
  • Publication number: 20080136468
    Abstract: Aspects of a method and system for signal processing are disclosed and may include using a frequency doubler to double the frequency of a reference signal utilized by a phase-frequency detector (PFD) in a fractional-N phase-locked-loop (PLL) synthesizer. Detecting and correcting a digital reference signal connected to the input of the frequency doubler. The digital reference signal may be generated by amplifying the difference between a low slew-rate reference signal and a reference voltage through a comparator. The reference voltage signal may be generated based on the detected duty-cycle of the digital reference signal. The duty-cycle of the digital reference signal may be adjusted by varying the generated reference voltage signal. The reference voltage may be generated by using difference of DC level of the digital reference signal and half rail. The reference voltage signal may be generated using a voltage digital-to-analog converter (DAC).
    Type: Application
    Filed: December 29, 2006
    Publication date: June 12, 2008
    Inventors: Dandan Li, Arya Behzad
  • Publication number: 20080139150
    Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 12, 2008
    Inventors: Qiang Li, Razieh Roufoogaran, Arya Behzad, Dandan Li, Hung-Ming Chien
  • Publication number: 20080136533
    Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 12, 2008
    Inventor: Dandan Li
  • Publication number: 20080136540
    Abstract: Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 12, 2008
    Inventor: Dandan Li
  • Publication number: 20070279135
    Abstract: A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 6, 2007
    Inventors: Christopher Hull, Russell Fagg, Dandan Li
  • Patent number: 7053683
    Abstract: A method and circuit for selecting the band of a multi-band voltage controlled oscillator in a phase locked loop is described. In one implementation, the circuit comprises a voltage controlled oscillator, a selection circuit for selecting a band for the voltage controlled oscillator from a plurality of predetermined bands, a decision circuit for determining if the selection circuit should select a new band from the plurality of predetermined bands, and a charging circuit for adjusting the input voltage into the voltage controlled oscillator.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 30, 2006
    Assignee: Agere Systems Inc.
    Inventor: Dandan Li
  • Publication number: 20050264330
    Abstract: A method and circuit for selecting the band of a multi-band voltage controlled oscillator in a phase locked loop is described. In one implementation, the circuit comprises a voltage controlled oscillator, a selection circuit for selecting a band for the voltage controlled oscillator from a plurality of predetermined bands, a decision circuit for determining if the selection circuit should select a new band from the plurality of predetermined bands, and a charging circuit for adjusting the input voltage into the voltage controlled oscillator.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 1, 2005
    Applicant: Agere Systems Inc.
    Inventor: Dandan Li
  • Patent number: 6888484
    Abstract: Stable, robust, and high-resolution delta-sigma error feedback modulators, such as those used in digital-to-analog converters and phase-locked loops, include an L-order noise transfer function that is provided with L+1 high-order bits from a truncation element. The stability of such delta-sigma error feedback modulators is independent of the input signal. Moreover, the out-of-band gain of the noise transfer function need not be limited, which improves the resolution and the signal-to-noise ratio of the in-band signal.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: May 3, 2005
    Assignee: Agere Systems Inc.
    Inventors: Peter Kiss, Jesus Arias, Dandan Li
  • Publication number: 20040233086
    Abstract: Stable, robust, and high-resolution delta-sigma error feedback modulators, such as those used in digital-to-analog converters and phase-locked loops, include an L-order noise transfer function that is provided with L+1 high-order bits from a truncation element. The stability of such delta-sigma error feedback modulators is independent of the input signal. Moreover, the out-of-band gain of the noise transfer function need not be limited, which improves the resolution and the signal-to-noise ratio of the in-band signal.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 25, 2004
    Inventors: Peter Kiss, Jesus Arias, Dandan Li
  • Patent number: 6137375
    Abstract: A circuit for controlling the loss of a VCO in a master-slave tuning system includes an envelope detector, an amplitude regulator, a current-mode circuit, and a low-pass filter. The envelope detector receives the VCO output voltage and provides VCO output envelope voltage, V.sub.ENV. The amplitude regulator receives V.sub.ENV and a reference voltage, V.sub.REF, and provides a sourcing current if V.sub.ENV is less than V.sub.REF, and draws a sinking current if V.sub.ENV is greater than V.sub.REF. The current-mode circuit receives V.sub.ENV and provides a control current, I.sub.Q. The low-pass filter has high DC gain for integrating the control current and the sourcing or sinking current to provide the VCO control voltage, V.sub.CON, to the VCO. The control current, I.sub.Q, is proportional to the inverse of V.sub.ENV multiplied by the time derivative of V.sub.ENV.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: October 24, 2000
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: Dandan Li