Patents by Inventor Dandan Zhu

Dandan Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250034080
    Abstract: A novel type of cationic lipid and PEGylated derivative thereof, a cationic liposome and a cationic liposome-nucleic acid pharmaceutical composition containing the cationic lipid and formulation thereof include an ionizable lipid compound of the general formula (1). This compound is slightly ionized or neutral at physiological pH but undergoes greater ionization under acidic conditions, exhibiting lower toxicity in the systemic circulation and improved endosomal escape ability. The compound's polar head contains an ionizable tertiary amine group along with a side chain containing functional groups, while the tail chains may include linking groups that are easily degraded. Cationic liposomes containing the compound have a better ability to complex with nucleic acid drugs, higher stability in serum, no apparent cytotoxicity, and high transfection efficiency.
    Type: Application
    Filed: January 1, 2023
    Publication date: January 30, 2025
    Applicant: XIAMEN SINOPEG BIOTECH CO., LTD.
    Inventors: Sheng LIN, Minggui LIN, Dandan CHEN, Ailan WANG, Congming LIN, Qi ZHU, Wengui WENG, Chao LIU, Jinchun YUAN
  • Patent number: 12166733
    Abstract: An information display method, an information display apparatus, and an electronic device are provided. The information display method includes: acquiring a first interactive message card forwarded by a first terminal device, where the first interactive message card displayed by the first terminal device includes a data submission control element used to collect user data in response to an user interaction operation and send the collected user data to another electronic device; generating a second interactive message card based on the first interactive message card, where a data submission control element in the second interactive message card does not have a data collection function; and displaying the second interactive message card.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: December 10, 2024
    Assignee: BEIJING ZITIAO NETWORK TECHNOLOGY CO., LTD.
    Inventors: Xin Zhang, Yafeng Miao, Hengyou Cai, Lun Li, Zeyao Yuan, Yanqing Wang, Lingwei Meng, Dandan Zhu, Wenjing Duan, Hongye Qi, Xianliang Li, Hongying Lu
  • Patent number: 11994923
    Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liu Yi, Dandan Zhu, Yuan Deng, Congyu Zhang, Neng-Hsien Lin, Tsung-Tao Wu, Fan-Hau Hsu
  • Publication number: 20230353515
    Abstract: An information display method, an information display apparatus, and an electronic device are provided. The information display method includes: acquiring a first interactive message card forwarded by a first terminal device, where the first interactive message card displayed by the first terminal device includes a data submission control element used to collect user data in response to an user interaction operation and send the collected user data to another electronic device; generating a second interactive message card based on the first interactive message card, where a data submission control element in the second interactive message card does not have a data collection function; and displaying the second interactive message card.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventors: Xin ZHANG, Yafeng MIAO, Hengyou CAI, Lun LI, Zeyao YUAN, Yanqing WANG, Lingwei MENG, Dandan ZHU, Wenjing DUAN, Hongye QI, Xianliang LI, Hongying LU
  • Publication number: 20230079748
    Abstract: The present disclosure relates to methods of preparing circulating tumor DNA (ctDNA) reference samples including: inducing apoptosis in tumor cells to obtain DNA fragments and then extracting DNA from the tumor cells to obtain the circulating tumor DNA reference samples. The methods to prepare ctDNA reference samples disclosed herein are simple and easy to use, suitable for various tumor cells, and the variant information can be retained to simulate the ctDNA in animals. In some embodiments, the reference samples can facilitate assay calibration and evaluation.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 16, 2023
    Inventors: Guolin Zhong, Mao Mao, Shiyong Li, Dandan Zhu, Yan Chen, Yumin Feng, Wei Wu
  • Publication number: 20230015133
    Abstract: Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.
    Type: Application
    Filed: June 3, 2020
    Publication date: January 19, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Dandan Zhu
  • Publication number: 20230006091
    Abstract: This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.
    Type: Application
    Filed: June 11, 2020
    Publication date: January 5, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Dandan Zhu, Liyang Zhang, Kai Cheng
  • Publication number: 20230004202
    Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.
    Type: Application
    Filed: May 17, 2022
    Publication date: January 5, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: LIU YI, DANDAN ZHU, YUAN DENG, CONGYU ZHANG, Neng-Hsien Lin, Tsung-Tao Wu, Fan-Hau Hsu
  • Patent number: 9705031
    Abstract: A semiconductor wafer comprising a substrate; a first AlGaN layer on the substrate; a second AlGaN layer on the first AlGaN layer; a GaN layer on the second AlGaN layer; and a plurality of crystalline GaN islands between the first and second AlGaN layers.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 11, 2017
    Assignee: Intellec Limited
    Inventors: Menno Kappers, Dandan Zhu
  • Publication number: 20150280058
    Abstract: A semiconductor wafer comprising a substrate; a first AlGaN layer on the substrate; a second AlGaN layer on the first AlGaN layer; a GaN layer on the second AlGaN layer; and a plurality of crystalline GaN islands between the first and second AlGaN layers.
    Type: Application
    Filed: October 2, 2013
    Publication date: October 1, 2015
    Applicant: Intellec Limited
    Inventors: Menno Kappers, Dandan Zhu
  • Patent number: 9142723
    Abstract: A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 22, 2015
    Assignee: Intellec Limited
    Inventors: Colin Humphreys, Clifford McAleese, Menno Kappers, Zhenyu Liu, Dandan Zhu
  • Publication number: 20130270575
    Abstract: A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.
    Type: Application
    Filed: October 12, 2011
    Publication date: October 17, 2013
    Inventors: Colin Humphreys, Clifford McAleese, Menno Kappers, Zhenyu Liu, Dandan Zhu