Patents by Inventor Dandan Zhu
Dandan Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12166733Abstract: An information display method, an information display apparatus, and an electronic device are provided. The information display method includes: acquiring a first interactive message card forwarded by a first terminal device, where the first interactive message card displayed by the first terminal device includes a data submission control element used to collect user data in response to an user interaction operation and send the collected user data to another electronic device; generating a second interactive message card based on the first interactive message card, where a data submission control element in the second interactive message card does not have a data collection function; and displaying the second interactive message card.Type: GrantFiled: July 3, 2023Date of Patent: December 10, 2024Assignee: BEIJING ZITIAO NETWORK TECHNOLOGY CO., LTD.Inventors: Xin Zhang, Yafeng Miao, Hengyou Cai, Lun Li, Zeyao Yuan, Yanqing Wang, Lingwei Meng, Dandan Zhu, Wenjing Duan, Hongye Qi, Xianliang Li, Hongying Lu
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Publication number: 20240294445Abstract: A continuous process for preparing exo-THDCPD by isomerization of endo-THDCPD includes the step of passing endo-THDCPD and hydrogen gas successively through a first reaction zone filled with a hydrogenation protectant and a second reaction zone filled with an isomerization catalyst to perform a hydroisomerization reaction so as to obtain exo-THDCPD, wherein the hydrogenation protectant is a supported metal hydrogenation catalyst, and the isomerization catalyst is a metal-modified molecular sieve catalyst. The process converts endo-THDCPD to exo-THDCPD, with a conversion of greater than 86% and a target product selectivity of greater than 94%.Type: ApplicationFiled: September 23, 2022Publication date: September 5, 2024Inventors: Zhaolin FU, Zhiping TAO, Enhui XING, Yibin LUO, Xingtian SHU, Jie ZHAO, Rui YAN, Dandan JIA, Zhongpeng ZHU, Weiping ZHENG
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Publication number: 20240287063Abstract: The present invention provides a methionine adenosyltransferase 2A inhibitor. The structure of the methionine adenosyltransferase 2A inhibitor is as represented by general formula (I), and the definitions of substituents are as described in the specification. The present invention further provides a preparation method therefor. A compound represented by formula I provided by the present invention has significant methionine adenosyltransferase 2A inhibitory activity, and can be used in the treatment of diseases mediated by overexpression of methionine adenosyltransferase 2A.Type: ApplicationFiled: May 31, 2022Publication date: August 29, 2024Applicant: NANJING CHIA TAI TIANQING PHARMACEUTICAL CO., LTD.Inventors: Changyou MA, Dandan HUANG, Jincai SU, Li MA, Yebin Wu, Qingyu DAI, Huan ZHANG, Rui Zuo, Qiuhua ZHOU, Jian WU, Lei MIAO, Dan XU, Chunxia ZHU, Zhoushan TIAN
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Patent number: 11994923Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.Type: GrantFiled: May 17, 2022Date of Patent: May 28, 2024Assignee: Realtek Semiconductor Corp.Inventors: Liu Yi, Dandan Zhu, Yuan Deng, Congyu Zhang, Neng-Hsien Lin, Tsung-Tao Wu, Fan-Hau Hsu
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Publication number: 20230353515Abstract: An information display method, an information display apparatus, and an electronic device are provided. The information display method includes: acquiring a first interactive message card forwarded by a first terminal device, where the first interactive message card displayed by the first terminal device includes a data submission control element used to collect user data in response to an user interaction operation and send the collected user data to another electronic device; generating a second interactive message card based on the first interactive message card, where a data submission control element in the second interactive message card does not have a data collection function; and displaying the second interactive message card.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Xin ZHANG, Yafeng MIAO, Hengyou CAI, Lun LI, Zeyao YUAN, Yanqing WANG, Lingwei MENG, Dandan ZHU, Wenjing DUAN, Hongye QI, Xianliang LI, Hongying LU
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Publication number: 20230079748Abstract: The present disclosure relates to methods of preparing circulating tumor DNA (ctDNA) reference samples including: inducing apoptosis in tumor cells to obtain DNA fragments and then extracting DNA from the tumor cells to obtain the circulating tumor DNA reference samples. The methods to prepare ctDNA reference samples disclosed herein are simple and easy to use, suitable for various tumor cells, and the variant information can be retained to simulate the ctDNA in animals. In some embodiments, the reference samples can facilitate assay calibration and evaluation.Type: ApplicationFiled: September 1, 2022Publication date: March 16, 2023Inventors: Guolin Zhong, Mao Mao, Shiyong Li, Dandan Zhu, Yan Chen, Yumin Feng, Wei Wu
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Publication number: 20230015133Abstract: Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.Type: ApplicationFiled: June 3, 2020Publication date: January 19, 2023Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Dandan Zhu
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Publication number: 20230006091Abstract: This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.Type: ApplicationFiled: June 11, 2020Publication date: January 5, 2023Applicant: ENKRIS SEMICONDUCTOR, INC.Inventors: Dandan Zhu, Liyang Zhang, Kai Cheng
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Publication number: 20230004202Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.Type: ApplicationFiled: May 17, 2022Publication date: January 5, 2023Applicant: Realtek Semiconductor Corp.Inventors: LIU YI, DANDAN ZHU, YUAN DENG, CONGYU ZHANG, Neng-Hsien Lin, Tsung-Tao Wu, Fan-Hau Hsu
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Patent number: 9705031Abstract: A semiconductor wafer comprising a substrate; a first AlGaN layer on the substrate; a second AlGaN layer on the first AlGaN layer; a GaN layer on the second AlGaN layer; and a plurality of crystalline GaN islands between the first and second AlGaN layers.Type: GrantFiled: October 2, 2013Date of Patent: July 11, 2017Assignee: Intellec LimitedInventors: Menno Kappers, Dandan Zhu
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Publication number: 20150280058Abstract: A semiconductor wafer comprising a substrate; a first AlGaN layer on the substrate; a second AlGaN layer on the first AlGaN layer; a GaN layer on the second AlGaN layer; and a plurality of crystalline GaN islands between the first and second AlGaN layers.Type: ApplicationFiled: October 2, 2013Publication date: October 1, 2015Applicant: Intellec LimitedInventors: Menno Kappers, Dandan Zhu
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Patent number: 9142723Abstract: A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.Type: GrantFiled: October 12, 2011Date of Patent: September 22, 2015Assignee: Intellec LimitedInventors: Colin Humphreys, Clifford McAleese, Menno Kappers, Zhenyu Liu, Dandan Zhu
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Publication number: 20130270575Abstract: A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.Type: ApplicationFiled: October 12, 2011Publication date: October 17, 2013Inventors: Colin Humphreys, Clifford McAleese, Menno Kappers, Zhenyu Liu, Dandan Zhu