Abstract: The present invention discloses a microminiature image acquisition and processing system package structure and a preparation method thereof. This structure includes optical coated glass, a CMOS chip, a wafer Re-Distribution Layer and a molding layer, the first surface of the CMOS chip is provided with a photosensitive and microlens region and a metal bonding pad, and a through-silicon via is etched in a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface; the wafer Re-Distribution Layer covers the second surface of the CMOS chip and extends to the through-silicon via. The structure and the method of the present invention are integrated with wafer-level package and SIP integrated package technologies to achieve single package of the whole device, thereby greatly reducing the system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference capability.

Abstract: The present invention provides a package structure with an inductor and a manufacturing method thereof, the inductor and the interconnection component are used as n second package module, and stacked with other components such as the first package module to form a stack-like package structure. The first package module is provided with other electronic elements. Then the first and second package modules can be synchronously subjected to package manufacturing, which improves the production efficiency. Additionally, the soldering balls with different heights are formed on the first faces of the interconnecting structural component and the inductive device by adjusting the consumption of soldering paste, which make the second faces of the inductor and the interconnection component are coplanar, then inductor with different heights can form a flat interconnecting plane, which makes the sequential process such as pasting and mounting can be conveniently performed.

Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

Abstract: The present invention provides an antenna packaging structure and a manufacturing method thereof. An antenna and a chip are respectively disposed on two sides of a substrate layer, antenna layers are formed by an antenna support member, a first antenna layer located above the antenna support member and a second antenna layer located below the antenna support member together, and interlayer dielectrics of the antenna support member and the antenna layers are low dielectric loss materials, so that a heterogeneous and isomerous antenna structure is formed, thereby reducing the problems such as current leakage and stray capacitance in the packaging structure caused by dielectric loss, and reducing a size of the antenna packaging structure.

Abstract: The present invention provides a fan-out packaging structure and a manufacturing method thereof. The packaging structure includes a redistribution layer, at least one plastic packaging layer, at least one first shielding layer, at least one chip, and at least one electrical connector. The redistribution layer includes a grounding line layer, and the chip and the electrical connector are disposed on a first face of the redistribution layer and are electrically connected to the redistribution layer; the plastic packaging layer encapsulates the electrical connector and the chip; the first shielding layer at least covers a side face of the plastic packaging layer; and the electrical connector is at least partially exposed to the side face of the plastic packaging layer and electrically connected to the first shielding layer.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes an interposer, chips, and warpage adjustment structures, wherein the interposer includes a first surface and a second surface opposite thereto, and the chips are electrically connected to the first surface of the interposer; the warpage adjustment structures are symmetrically distributed with respect to a center of the first surface; and each of the warpage adjustment structures include a warpage adjustment piece and/or a cavity filled with a plastic packaging material, the warpage adjustment piece is disposed on the first surface, and the cavity is located outside conducting structures and sinks inward along the first surface. By cooperation between the warpage adjustment pieces and the cavities filled with the plastic packaging material, the warpage of the interposer in horizontal and vertical directions can be reduced.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package and an upper package; wherein the lower package includes a prefabricated interconnected silicon core stack structure which includes a silicon interconnection layer, and the silicon interconnection layer includes a first surface and a second surface; a back-end redistribution stack layer and a first prefabricated redistribution stack layer are stacked on the first surface and in electrical connection; a passivation layer is disposed on the second surface; the silicon interconnection layer includes a silicon substrate and several first prefabricated conductive pillars, each first prefabricated conductive pillar includes a first end and a second end, the first end is exposed from the first surface, and the second end is exposed from a side of the passivation layer; and the upper package is disposed above the first prefabricated redistribution stack layer.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes: a lower package, an upper package disposed above the lower package, and a first redistribution stack layer that is disposed between the lower package and the upper package and is electrically connected to the lower package and the upper package. The lower package includes a first prefabricated redistribution stack layer and a first plastic packaging layer surrounding the first prefabricated redistribution stack layer. A minimum line width and line spacing of at least one first prefabricated conductive layer in the first prefabricated redistribution stack layer is less than a minimum line width and line spacing of at least one first conductive layer in the first redistribution stack layer.

Abstract: The present invention provides a fan-out package structure and a method for manufacturing the same. The fan-out package structure includes at least one chip and at least one redistribution layer on a functional surface side of the chip, and the redistribution layer includes a dielectric layer and a metal wiring layer distributed within the dielectric layer. The fan-out package structure further includes at least one dummy wafer on the redistribution layer, and the dummy wafer is insulated from the chip and in contact with the metal wiring layer. By providing the dummy wafer on the redistribution layer and configuring the dummy wafer to connect to the metal wiring layer, the dummy wafer can not only function to support the structure and suppress the warpage, but also form a continuous heat dissipation channel, thereby improving thermal management capability of the fan-out package structure.

Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

Abstract: The present invention provides an SIP package structure. The SIP package structure comprises a first module, a second module and a shielding assembly, wherein the first module and the second module are horizontally distributed or vertically stacked; electromagnetic sensitive frequencies of the first module and the second module are different; the shielding assembly comprises a first shielding structure covering the first module and a second shielding structure covering the second module; and at least part of the first shielding structure and/or at least part of the second shielding structure are/is disposed between the first module and the second module.