Abstract: Methods and systems for providing financial and/or board member information in a secured manner to members of boards of directors of companies and others through a publicly-available widely disseminated network.

Abstract: An integrated circuit is provided with built-in-self test circuitry. The integrated circuit may have multiple blocks of memory. The memory may be tested using the built-in-self test circuitry. Each memory block may include a satellite address generator that is used in generating test addresses for the memory blocks. Each memory block may also include failure analysis logic and output response analyzer logic. Stalling logic may be used to individually stall memory block testing on a block-by-block basis during memory tests. Address buffer circuitry such as first-in-first-out buffers may be used to provide randomized memory addresses during testing.

Abstract: An integrated circuit is provided with built-in-self test circuitry. The integrated circuit may have multiple blocks of memory. The memory may be tested using the built-in-self test circuitry. Each memory block may include a satellite address generator that is used in generating test addresses for the memory blocks. Each memory block may also include failure analysis logic and output response analyzer logic. Stalling logic may be used to individually stall memory block testing on a block-by-block basis during memory tests. Address buffer circuitry such as first-in-first-out buffers may be used to provide randomized memory addresses during testing.

Abstract: A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of the reconfigurable device. Additionally, the set of boundary scan registers only exists when a testing configuration is loaded into the reconfigurable device. When testing is complete, the testing configuration is erased and the functional blocks may implement other operations. Thus, the set of boundary scan registers consumes no additional chip area. Furthermore, as the set of boundary scan registers disappears after testing, a functional path enabling normal operation modes is unnecessary. Therefore, manually created functional test data is not needed. Instead, ATPG software can create test data from hardware descriptions of the IP core and the set of boundary scan registers.