Abstract: Embodiments of the present disclosure include an apparatus comprising an electronic device, a first magnet, and an inductive coil surrounding a magnetically susceptible core, wherein movement of the first magnet relative to the magnetically susceptible core changes a magnetic flux in the magnetically susceptible core to produce a current in the inductive coil, and in accordance therewith, provide power to the electronic device.

Abstract: Embodiments of the present disclosure include an apparatus comprising an electronic device, a first magnet, and an inductive coil surrounding a magnetically susceptible core, wherein movement of the first magnet relative to the magnetically susceptible core changes a magnetic flux in the magnetically susceptible core to produce a current in the inductive coil, and in accordance therewith, provide power to the electronic device.

Abstract: Embodiments of the present disclosure pertain to low frequency pressure sensing. In one embodiment, the present disclosure includes an apparatus comprising a pressure sensor having at least one input and a chamber. The chamber is coupled to the input of the pressure sensor to control pressure variations sensed by the pressure sensor. The chamber comprises a hole, where the hole and the chamber are configured to low pass filter pressure variations at the input of the pressure sensor and filter out pressure variations above about 20 hertz.

Abstract: An improved system for concurrently running multiple virtual machines on a single processor. Each virtual machine being activated only during an assigned time slice or partition so as to isolate each of the concurrently running virtual machines from each other. The system having a power management mode and/or a partition reassignment mode. The power management feature placing the processor into a reduced power mode when a particular virtual machine has nothing to do during its assigned partition. In one embodiment, when an application has not been loaded into a given virtual machine, the processor is placed into a reduced power mode during the partition assigned to the given virtual machine. In one embodiment, the virtual machine is a JAVA Virtual Machine.

Abstract: A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.

Abstract: For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ("A"), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and "delay" the parameter represented by the state of signals externally developed on a "DA" bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for "bit-reverse order" addressing; and a unit for "rounding off" certain results.

Abstract: The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.