Abstract: A receiver for satellite navigation includes a signal processor for deriving from a satellite signal a pseudorandom sequence of code chips, a converter for producing a digitized version of the received PRN sequence, a first and second shift register (3, 7), a code generator (4), a set of correlators, circuitry for summing correlation values and circuitry for determining a maximum of the summed correlation, and a scheduler (20). The receiver includes at least one multiplexer (6, 24), configured to transform multiple PRN sequences into an interleaved sequence and to enter the interleaved sequence into the first or second shift register (3, 7). The summing circuitry has multiple summing circuits (11) for separately summing correlation values related to the multiple PRN sequences. The circuitry for determining a maximum is configured to determine the maximum in one or more subgroups of sums determined by the multiple summing circuits (11).

Abstract: A hybrid circuit that couples a broadband modem to a POTS or ISDN telecommunication line (TL) and includes a transformer bridge circuit (TBC) that includes a bridge circuit (BC). The bridge circuit includes four legs formed by impedance matching networks and parts of the transformer, and a differential drive amplifier (DRV) that performs impedance synthesis. A secondary winding (TS) of the transformer is magnetically coupled to the first and the second primary windings and is electrically coupled to the telecommunication line. First and second impedance dividers (Zhin1, Zhout1 and Zhin2, Zhout2) are connected to the various nodes to provide outputs to a receive amplifier (RCV). The impedance matching networks (Zm1; Zm2) include various passive and reactive components that together provide an impedance value selected based upon the line impedance reflected into the primary windings (TP1; TP2) of the transformer.

Abstract: A hybrid circuit that couples a broadband modem to a POTS or ISDN telecommunication line (TL) and includes a transformer bridge circuit (TBC) that includes a bridge circuit (BC). The bridge circuit includes four legs formed by impedance matching networks and parts of the transformer, and a differential drive amplifier (DRV) that performs impedance synthesis. A secondary winding (TS) of the transformer is magnetically coupled to the first and the second primary windings and is electrically coupled to the telecommunication line. First and second impedance dividers (Zhin1, Zhout1 and Zhin2, Zhout2) are connected to the various nodes to provide outputs to a receive amplifier (RCV). The impedance matching networks (Zm1; Zm2) include various passive and reactive components that together provide an impedance value selected based upon the line impedance reflected into the primary windings (TP1; TP2) of the transformer.

Abstract: A hybrid circuit that couples a broadband modem to a POTS or ISDN telecommunication line (TL) and comprises a transformer bridge circuit (TBC) that includes a bridge circuit (BC). The bridge circuit is constituted by four legs of which a first (A) and a second (B) nodes, that do not belong to a same leg, are connected to the two outputs of a differential drive amplifier (DRV) that performs impedance synthesis. A first leg is made of a first impedance matching network (Zm1) connected between the second node (B) and a third node (C). A second leg is made of a first primary winding (TP1) of a transformer and is connected between the third (C) and the first (A) nodes. A third leg is made of a second impedance matching network (Zm2) connected between the first node (A) and a fourth node (D). A forth leg is made of a second primary winding (TP2) of the transformer and is connected between the fourth (D) and second (B) nodes.

Abstract: A hybrid circuit that couples a broadband modem to a POTS or ISDN telecommunication line (TL) and comprises a transformer bridge circuit (TBC) that includes a bridge circuit (BC). The bridge circuit is constituted by four legs of which a first (A) and a second (B) nodes, that do not belong to a same leg, are connected to the two outputs of a differential drive amplifier (DRV) that performs impedance synthesis. A first leg is made of a first impedance matching network (Zm1) connected between the second node (B) and a third node (C). A second leg is made of a first primary winding (TP1) of a transformer and is connected between the third (C) and the first (A) nodes. A third leg is made of a second impedance matching network (Zm2) connected between the first node (A) and a fourth node (D). A forth leg is made of a second primary winding (TP2) of the transformer and is connected between the fourth (D) and second (B) nodes.

Abstract: A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers. The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only a 3 Volt battery supply as used in wireless phones. The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.

Abstract: A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT).

Abstract: A level converts circuit converting a digital input signal varying between a first (VSS) and a second (VDD1) voltage level to a digital output signal varying between the first (VSS) and a third voltage. (VDD2) the local conversion circuit includes between first (VDD2) and second (VSS) poles of a DC supply source a series connection of a load impedance (P2/P3/N3) and the main paths of a first transistor (N2) and of a second transistor (N1), to a control electrode of which the input signal is applied. The first and second transistor are of a same first conductivity type. A third transistor (P1) of a second conductivity type is connected in parallel with the second transistor (N1). A control electrode of the third (P1) and first (N2) transistors are biased by a constant DC bias voltage (VBIAS1A/VBIAS1B), and a junction point of the load impedance (P2/P3/N3) and the series connection being an output terminal (OUT) of the level conversion circuit.

Abstract: The direct conversion receiver DCR receives analog modulating signals with a reference average value and modulated within assigned time slots of a TDMA-structure on a carrier with a carrier frequency FC which changes from time slot to time slot. DCR includes a demodulator circuit DC-coupled to a baseband circuit, the demodulator circuit including a local oscillator LO and a mixer MIX and the baseband circuit including an offset correction circuit OCC/OCC' for updating different variable parameter offset correction values for different FC stored in a memory MEM and compensating offset introduced in DCR. OCC/OCC' determines, upon occurrence of an assigned time slot, an updated offset correction value as a function of an old offset correction value in a corresponding storage location of MEM and the difference between an average value of the analog signal and the reference average value, and thereupon stores the result in the corresponding storage place.

Abstract: A data transmission system is proposed in which an auxiliary bitstream of low bitrate (AUX) is coded together with a main bitstream of high bitrate (PRIM) without increasing the transmission rate above the high bitrate. This auxiliary bitstream (AUX) is moreover transmitted synchronously with the main bitstream (PRIM). Transmitter (T) divides the main bitstream (PRIM) in periodically occurring blocks of Y bits and codes one bit of the auxiliary bitstream (AUX) in each of the blocks by using a first (AMI) or a second (VAMI) coding law according to the binary value of that bit. The second law is constructed by violating the first coding law (AMI) according to a predetermined violation law. Redundancy in the first coding law (AMI) is used to introduce symbol sequences not permitted under this first coding law (AMI) and to so obtain the second coding law (VAMI).

Abstract: A signal persistence time interval recognition system reproduces a condition of an input signal as a condition of an output signal only when the input signal condition persists for at least a predetermined time interval. The system periodically scans the input signal condition and has a first memory (ROM) for storing a start value indicative of the time interval. A second memory (RAM) stores a value indicative of the time counted since the detection of a difference between the input and output signal conditions. A third memory stores the output signal condition and a processor brings the start value from the first memory into the second memory when no difference is detected. The processor modifies the value in the second memory each time such a difference is detected and until a value is reached indicating that the time interval has been counted, the output signal condition in the third memory being then changed.

Abstract: An echo canceller, using an Adaptive Finite Input Response Filter (AFIR), uses a processing device with a plurality of interconnected cells. These cells, connected in a systolic arrangement, determines the function of three variables m, n, and p, in the equation p+m n, where m and n are data inputs to each of the cells, and p is the output of a previous calculation cell. This is achieved by using a timing sequence, in which the variable m is applied bit serial to the cells over a period of q time slots, and the variable n is applied in parallel over the cells in one time slot.