Patents by Inventor Dani Voitsechov
Dani Voitsechov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103912Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Inventors: Yoav Etsion, Dani Voitsechov
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Publication number: 20240086371Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
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Patent number: 11900156Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.Type: GrantFiled: September 9, 2020Date of Patent: February 13, 2024Assignee: SPEEDATA LTD.Inventors: Yoav Etsion, Dani Voitsechov
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Patent number: 11874800Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.Type: GrantFiled: January 16, 2023Date of Patent: January 16, 2024Assignee: SPEEDATA LTD.Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
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Publication number: 20230153273Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.Type: ApplicationFiled: January 16, 2023Publication date: May 18, 2023Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
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Patent number: 11586587Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.Type: GrantFiled: September 24, 2020Date of Patent: February 21, 2023Assignee: SPEEDATA LTD.Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
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Patent number: 11354157Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.Type: GrantFiled: April 28, 2020Date of Patent: June 7, 2022Assignee: SPEEDATA LTD.Inventors: Dani Voitsechov, Yoav Etsion
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Publication number: 20220092030Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.Type: ApplicationFiled: September 24, 2020Publication date: March 24, 2022Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
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Patent number: 11175922Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.Type: GrantFiled: June 1, 2020Date of Patent: November 16, 2021Assignee: SPEEDATA LTD.Inventors: Yoav Etsion, Dani Voitsechov, Evgeni Krimer, Jonathan Friedmann
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Publication number: 20210334134Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Dani Voitsechov, Yoav Etsion
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Publication number: 20210334106Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.Type: ApplicationFiled: June 1, 2020Publication date: October 28, 2021Inventors: Yoav Etsion, Dani Voitsechov, Evgeni Krimer, Jonathan Friedmann
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Patent number: 11003458Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.Type: GrantFiled: January 27, 2020Date of Patent: May 11, 2021Assignee: SPEEDATA LTD.Inventors: Yoav Etsion, Dani Voitsechov
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Publication number: 20210089349Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.Type: ApplicationFiled: September 9, 2020Publication date: March 25, 2021Inventors: Yoav Etsion, Dani Voitsechov
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Publication number: 20200159539Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Inventors: Yoav Etsion, Dani Voitsechov
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Patent number: 10579390Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.Type: GrantFiled: December 3, 2017Date of Patent: March 3, 2020Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD.Inventors: Yoav Etsion, Dani Voitsechov
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Publication number: 20180101387Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.Type: ApplicationFiled: December 3, 2017Publication date: April 12, 2018Inventors: Yoav Etsion, Dani Voitsechov
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Publication number: 20150268963Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.Type: ApplicationFiled: March 10, 2015Publication date: September 24, 2015Inventors: Yoav Etsion, Dani Voitsechov