Patents by Inventor Danial S. Dean

Danial S. Dean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Zero-enabled fuse-set
    Patent number: 7139209
    Abstract: A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: November 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Frank Alejano, Brian J. Ladner, Timothy B. Cowles, Todd A. Merrit, Danial S. Dean, Paul M. Prew
  • Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6985393
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Zero-enabled fuse-set
    Patent number: 6980478
    Abstract: A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: December 27, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Frank Alejano, Brian J. Ladner, Timothy B. Cowles, Todd A. Merritt, Danial S. Dean, Paul M. Prew
  • Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6829182
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: December 7, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Publication number: 20040027887
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Application
    Filed: August 4, 2003
    Publication date: February 12, 2004
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6611467
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: August 26, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Publication number: 20020186605
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 12, 2002
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6442086
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Publication number: 20020021607
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.
    Type: Application
    Filed: October 15, 2001
    Publication date: February 21, 2002
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6327201
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a VCC-to-ground voltage drop for the entire refresh interval.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: December 4, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Publication number: 20010038559
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage Vcc to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a Vcc-to-ground voltage drop for the entire refresh interval.
    Type: Application
    Filed: July 2, 2001
    Publication date: November 8, 2001
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6101139
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage V.sub.CC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a V.sub.CC -to-ground voltage drop for the entire refresh interval.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: August 8, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean
  • Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
    Patent number: 6002622
    Abstract: A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage V.sub.cc to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a V.sub.cc -to-ground voltage drop for the entire refresh interval.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: December 14, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Danial S. Dean