Patents by Inventor Daniel A. Boals
Daniel A. Boals has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940912Abstract: A logical-to-physical (L2P) table is maintained, wherein a plurality of sections of the L2P table is cached in a volatile memory device. A total dirty count for the L2P table is maintained, wherein the total dirty count reflects a total number of updates to the L2P table. Respective section dirty counts for the plurality of sections are maintained, wherein each respective section dirty count reflects a total number of updates to a corresponding section. It is determined that the total dirty count for the L2P table satisfies a threshold criterion. In response to determining that the total dirty count for the L2P table satisfies the threshold criterion, a first section of the plurality of sections is identified based on the respective section dirty counts. The first section of the L2P table is written to a non-volatile memory device.Type: GrantFiled: March 1, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Byron Harris, Daniel Boals, Abedon Madril
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Patent number: 11922011Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address.Type: GrantFiled: September 1, 2021Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Johnny A. Lam, Samyukta Mudugal, Sanjay Subbarao, Byron D. Harris, Daniel A. Boals
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Patent number: 11797435Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.Type: GrantFiled: June 7, 2021Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
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Patent number: 11762765Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.Type: GrantFiled: June 7, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
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Publication number: 20230289285Abstract: A journal count reflecting a number of logical-to-physical (L2P) journals written to a non-volatile memory device is maintained, wherein each L2P journal is associated with one or more updates to an L2P address mapping table. In response to determining that the journal count satisfies a threshold criterion, a first section of a plurality of sections of the L2P address mapping table is identified, wherein the plurality of sections of the L2P address mapping table is cached in a volatile memory device. The first section of the L2P address mapping table is written to the non-volatile memory device.Type: ApplicationFiled: May 23, 2023Publication date: September 14, 2023Inventors: Byron Harris, Daniel Boals, Abedon Madril
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Publication number: 20230281123Abstract: A logical-to-physical (L2P) table is maintained, wherein a plurality of sections of the L2P table is cached in a volatile memory device. A total dirty count for the L2P table is maintained, wherein the total dirty count reflects a total number of updates to the L2P table. Respective section dirty counts for the plurality of sections are maintained, wherein each respective section dirty count reflects a total number of updates to a corresponding section. It is determined that the total dirty count for the L2P table satisfies a threshold criterion. In response to determining that the total dirty count for the L2P table satisfies the threshold criterion, a first section of the plurality of sections is identified based on the respective section dirty counts. The first section of the L2P table is written to a non-volatile memory device.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventors: Byron Harris, Daniel Boals, Abedon Madril
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Patent number: 11714748Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.Type: GrantFiled: March 1, 2022Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Byron Harris, Daniel Boals, Abedon Madril
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Patent number: 11698746Abstract: An operation performed on a non-volatile memory device is detected. A type of the operation is determined. The type of the operation comprises a type identifier and a type modifier. A journal entry is generated reflecting the operation. The journal entry comprises a body reflecting the operation and a header comprising the type identifier and the type modifier. A combination of the type identifier and the type modifier define a size of the journal entry. The journal entry is written to a volatile memory device.Type: GrantFiled: March 1, 2022Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Tom V Geukens, Daniel A Boals
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Publication number: 20230061180Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Inventors: Johnny A. Lam, Samyukta Mudugal, Sanjay Subbarao, Byron D. Harris, Daniel A. Boals
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Patent number: 11334433Abstract: A first data location is identified, where the first data location is predetermined to store a first parity data based on a plurality of user data at a plurality of data locations of a storage system. A set of user data is stored at a subset of data locations of the plurality of data locations. A second parity data is stored at a memory buffer location. The second parity data is generated based on the set of user data. An indication of an occurrence of an event is received, the event associated with the storage system. In response to receiving the indication of the occurrence of the event, the second parity data is stored at a second data location external to the plurality of data locations. Upon restart of the storage system, the second parity data is transferred to a third data location of the plurality of data locations. The third data location is situated after the subset of the plurality of data locations and prior to the first data location.Type: GrantFiled: November 16, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventor: Daniel A. Boals
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Patent number: 11275523Abstract: A plurality of generators that each correspond to a respective one of a plurality of cursors associated with the plurality of memory devices are identified. A sequence of logical unit numbers (LUNs) of a plurality of sequences of LUNs are generated for each of the cursors based on a respective generator corresponding to the plurality of cursors. Each of the cursors are directed to perform a memory operation on a set of LUNs in an order provided by the sequence of LUNs that is associated with each of the plurality of cursors.Type: GrantFiled: October 23, 2020Date of Patent: March 15, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
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Publication number: 20210294751Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
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Patent number: 11030089Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.Type: GrantFiled: September 28, 2018Date of Patent: June 8, 2021Assignee: Micron Technology, Inc.Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
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Publication number: 20210073076Abstract: A first data location is identified, where the first data location is predetermined to store a first parity data based on a plurality of user data at a plurality of data locations of a storage system. A set of user data is stored at a subset of data locations of the plurality of data locations. A second parity data is stored at a memory buffer location. The second parity data is generated based on the set of user data. An indication of an occurrence of an event is received, the event associated with the storage system. In response to receiving the indication of the occurrence of the event, the second parity data is stored at a second data location external to the plurality of data locations. Upon restart of the storage system, the second parity data is transferred to a third data location of the plurality of data locations. The third data location is situated after the subset of the plurality of data locations and prior to the first data location.Type: ApplicationFiled: November 16, 2020Publication date: March 11, 2021Inventor: Daniel A. Boals
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Publication number: 20210042055Abstract: A plurality of generators that each correspond to a respective one of a plurality of cursors associated with the plurality of memory devices are identified. A sequence of logical unit numbers (LUNs) of a plurality of sequences of LUNs are generated for each of the cursors based on a respective generator corresponding to the plurality of cursors. Each of the cursors are directed to perform a memory operation on a set of LUNs in an order provided by the sequence of LUNs that is associated with each of the plurality of cursors.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
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Patent number: 10860243Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.Type: GrantFiled: November 30, 2018Date of Patent: December 8, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
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Patent number: 10838812Abstract: User data to be stored at a data block location of a plurality of data block locations at a storage system may be received. A parity data based on the received user data may be generated. An indication of an occurrence of an event associated with the storage system may be received. In response to receiving the indication of the occurrence of the event, the parity data may be stored by a processing device at a particular data block location of the plurality of data block locations where the particular data block location is situated prior to another data block location, of the plurality of data block locations, that is to store another parity data based on a subsequent user data.Type: GrantFiled: November 13, 2018Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventor: Daniel A. Boals
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Publication number: 20200174693Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
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Publication number: 20200151059Abstract: User data to be stored at a data block location of a plurality of data block locations at a storage system may be received. A parity data based on the received user data may be generated. An indication of an occurrence of an event associated with the storage system may be received. In response to receiving the indication of the occurrence of the event, the parity data may be stored by a processing device at a particular data block location of the plurality of data block locations where the particular data block location is situated prior to another data block location, of the plurality of data block locations, that is to store another parity data based on a subsequent user data.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Inventor: Daniel A. Boals
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Publication number: 20200104251Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel