Patents by Inventor Daniel A. Day
Daniel A. Day has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10337088Abstract: A method according to one embodiment includes combining an amorphous iron-based alloy and at least one metal selected from a group consisting of molybdenum, chromium, tungsten, boron, gadolinium, nickel phosphorous, yttrium, and alloys thereof to form a mixture, wherein the at least one metal is present in the mixture from about 5 atomic percent (at %) to about 55 at %; and ball milling the mixture at least until an amorphous alloy of the iron-based alloy and the at least one metal is formed. Several amorphous iron-based metal alloys are also presented, including corrosion-resistant amorphous iron-based metal alloys and radiation-shielding amorphous iron-based metal alloys.Type: GrantFiled: March 22, 2016Date of Patent: July 2, 2019Assignee: Lawrence Livermore National Security, LLCInventors: Cheng Kiong Saw, William A. Bauer, Jor-Shan Choi, Sumner Daniel Day, Joseph C. Farmer
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Patent number: 10216520Abstract: A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.Type: GrantFiled: December 12, 2014Date of Patent: February 26, 2019Assignee: VIA TECHNOLOGIES, INC.Inventors: Matthew Daniel Day, G. Glenn Henry, Terry Parks
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Patent number: 9588769Abstract: A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.Type: GrantFiled: June 25, 2014Date of Patent: March 7, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Matthew Daniel Day
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Publication number: 20160201176Abstract: A method according to one embodiment includes combining an amorphous iron-based alloy and at least one metal selected from a group consisting of molybdenum, chromium, tungsten, boron, gadolinium, nickel phosphorous, yttrium, and alloys thereof to form a mixture, wherein the at least one metal is present in the mixture from about 5 atomic percent (at %) to about 55 at %; and ball milling the mixture at least until an amorphous alloy of the iron-based alloy and the at least one metal is formed.Type: ApplicationFiled: March 22, 2016Publication date: July 14, 2016Inventors: Cheng Kiong Saw, William A. Bauer, Jor-Shan Choi, Sumner Daniel Day, Joseph C. Farmer
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Publication number: 20160098277Abstract: A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue.Type: ApplicationFiled: December 12, 2014Publication date: April 7, 2016Inventors: MATTHEW DANIEL DAY, G. GLENN HENRY, TERRY PARKS
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Publication number: 20150347140Abstract: A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.Type: ApplicationFiled: June 25, 2014Publication date: December 3, 2015Inventors: Gerard M. Col, Matthew Daniel Day
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Patent number: 8930679Abstract: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.Type: GrantFiled: October 23, 2009Date of Patent: January 6, 2015Assignee: Via Technologies, Inc.Inventors: Matthew Daniel Day, Rodney E. Hooker
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Patent number: 8464029Abstract: An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue and populates the allocated entry with an instruction pointer of a load instruction, when it determines that the load instruction must be replayed. The RAT allocates an entry of the second queue when it encounters a store instruction and populates the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data. The RAT causes a subsequent instance of the load instruction to share the dependency when it encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.Type: GrantFiled: October 23, 2009Date of Patent: June 11, 2013Assignee: VIA Technologies, Inc.Inventors: Matthew Daniel Day, Rodney E. Hooker
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Patent number: 8409524Abstract: A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances.Type: GrantFiled: February 2, 2012Date of Patent: April 2, 2013Assignee: Lawrence Livermore National Security, LLCInventors: Joseph C. Farmer, James L. Brunk, S. Daniel Day
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Patent number: 8332618Abstract: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.Type: GrantFiled: December 9, 2009Date of Patent: December 11, 2012Assignee: VIA Technologies, Inc.Inventors: Gerard M. Col, Matthew Daniel Day, Terry Parks, Bryan Wayne Pogor
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Publication number: 20120135528Abstract: A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances.Type: ApplicationFiled: February 2, 2012Publication date: May 31, 2012Applicant: Lawrence Livermore National Security, LLCInventors: Joseph C. Farmer, James L. Brunk, S. Daniel Day
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Patent number: 8143063Abstract: A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances.Type: GrantFiled: July 16, 2010Date of Patent: March 27, 2012Assignee: Lawrence Livermore National Security, LLCInventors: Joseph C. Farmer, James L. Brunk, S. Daniel Day
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Publication number: 20110035573Abstract: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.Type: ApplicationFiled: December 9, 2009Publication date: February 10, 2011Applicant: VIA Technologies, Inc.Inventors: Gerard M. Col, Matthew Daniel Day, Terry Parks, Bryan Wayne Pogor
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Publication number: 20110008896Abstract: A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances.Type: ApplicationFiled: July 16, 2010Publication date: January 13, 2011Inventors: Joseph C. Farmer, James L. Brunk, S. Daniel Day
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Publication number: 20100306508Abstract: An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue and populates the allocated entry with an instruction pointer of a load instruction, when it determines that the load instruction must be replayed. The RAT allocates an entry of the second queue when it encounters a store instruction and populates the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data. The RAT causes a subsequent instance of the load instruction to share the dependency when it encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.Type: ApplicationFiled: October 23, 2009Publication date: December 2, 2010Applicant: VIA Technologies, Inc.Inventors: Matthew Daniel Day, Rodney E. Hooker
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Publication number: 20100306509Abstract: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold an instruction pointer of a load instruction and to hold information useable to identify a store instruction that caused the load instruction to be replayed on a first instance of the load instruction. A register alias table (RAT) encounters instructions in program order and generates dependencies used to determine when the instructions may execute out of program order. The RAT encounters the load instruction on a second instance, determines that the load instruction second instance instruction pointer matches the instruction pointer of an entry of the queue, and causes the load instruction on the second instance to have a dependency on the store instruction identified by the information in the matching entry.Type: ApplicationFiled: October 23, 2009Publication date: December 2, 2010Applicant: VIA Technologies, inc.Inventors: Matthew Daniel Day, Rodney E. Hooker
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Publication number: 20100306507Abstract: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.Type: ApplicationFiled: October 23, 2009Publication date: December 2, 2010Applicant: VIA Technologies, Inc.Inventors: Matthew Daniel Day, Rodney E. Hooker
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Publication number: 20100263766Abstract: A method according to one embodiment includes combining an amorphous iron-based alloy and at least one metal selected from a group consisting of molybdenum, chromium, tungsten, boron, gadolinium, nickel phosphorous, yttrium, and alloys thereof to form a mixture, wherein the at least one metal is present in the mixture from about 5 atomic percent (at %) to about 55 at %; and ball milling the mixture at least until an amorphous alloy of the iron-based alloy and the at least one metal is formed.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Inventors: Cheng Kiong Saw, William A. Bauer, Jor-Shan Choi, Sumner Daniel Day, Joseph C. Farmer
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Patent number: 7780912Abstract: A paint that warns of radiological or chemical substances comprising a paint operatively connected to the surface, an indicator material carried by the paint that provides an indication of the radiological or chemical substances, and a thermo-activation material carried by the paint. In one embodiment, a method of warning of radiological or chemical substances comprising the steps of painting a surface with an indicator material, and monitoring the surface for indications of the radiological or chemical substances. In another embodiment, a paint is operatively connected to a vehicle and an indicator material is carried by the paint that provides an indication of the radiological or chemical substances.Type: GrantFiled: December 1, 2005Date of Patent: August 24, 2010Assignee: Lawrence Livermore National Security, LLCInventors: Joseph C. Farmer, James L. Brunk, Sumner Daniel Day
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Publication number: 20100144024Abstract: A method of replica moulding microstructures, the method including forming a negative master of at least one microstructure configured to support microscopic biological material, casting a flowable polymeric material onto the negative master, placing a substrate against the flowable polymeric material and the negative master, allowing the flowable polymeric material to solidify in the negative master and on the substrate, and separating the substrate and the solidified polymeric material from the negative master, thereby leaving a positive replica of the at least one microstructure on the substrate.Type: ApplicationFiled: November 30, 2007Publication date: June 10, 2010Applicant: SWINBURNE UNIVERSITY OF TECHNOLOGYInventors: Daniel Day, Min Gu