Patents by Inventor Daniel A. Delibac
Daniel A. Delibac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9576863Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: GrantFiled: December 11, 2015Date of Patent: February 21, 2017Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Publication number: 20160181166Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: ApplicationFiled: December 11, 2015Publication date: June 23, 2016Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Patent number: 9330988Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: GrantFiled: December 23, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Patent number: 9087839Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.Type: GrantFiled: March 29, 2013Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Daniel A. Delibac, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Eric J. White
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Patent number: 9006703Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: GrantFiled: July 31, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Publication number: 20150035117Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Publication number: 20140291802Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Daniel A. Delibac, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Eric J. White
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Patent number: 8084864Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.Type: GrantFiled: May 24, 2011Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette
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Publication number: 20110221064Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Applicant: International Business Machines CorporationInventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette
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Patent number: 8003536Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.Type: GrantFiled: September 2, 2009Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette
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Publication number: 20100237503Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.Type: ApplicationFiled: September 2, 2009Publication date: September 23, 2010Applicant: International Business Machines CorporationInventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette
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Publication number: 20090230555Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.Type: ApplicationFiled: March 17, 2008Publication date: September 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Chapple-Sokol, Daniel A. Delibac, Zhong-Xiang He, Tom C. Lee, William J. Murphy, Timothy D. Sullivan, David C. Thomas, Daniel S. Vanslette