Patents by Inventor Daniel A. DOBSON

Daniel A. DOBSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9384835
    Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Daniel A. Dobson, Travis R. Hebig, Reid A. Wistort
  • Patent number: 8848414
    Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Daniel A. Dobson, Travis R. Hebig
  • Publication number: 20140112045
    Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, Daniel A. Dobson, Travis R. Hebig
  • Publication number: 20130326111
    Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor ARSOVSKI, Daniel A. DOBSON, Travis R. HEBIG, Reid A. WISTORT