Patents by Inventor Daniel A. Inns
Daniel A. Inns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10396229Abstract: A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.Type: GrantFiled: May 9, 2011Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Joel P. De Souza, Harold J. Hovel, Daniel A. Inns, Jeehwan Kim, Christian Lavoie, Devendra K. Sadana, Katherine L. Saenger, Davood Shahrjerdi, Zhen Zhang
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Patent number: 8933456Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.Type: GrantFiled: September 14, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, Katherine L. Saenger
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Publication number: 20140109961Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.Type: ApplicationFiled: January 2, 2014Publication date: April 24, 2014Applicant: International Business Machines CorporationInventors: Stephen W. Bedell, Harold J. Hovel, Daniel A. Inns, Jee H. Kim, Alexander Reznicek, Devendra K. Sadana
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Patent number: 8653360Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.Type: GrantFiled: August 4, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Harold J. Hovel, Daniel A. Inns, Jee H. Kim, Alexander Reznicek, Devendra K. Sadana
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Publication number: 20130015455Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.Type: ApplicationFiled: September 14, 2012Publication date: January 17, 2013Applicant: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Daniel A. Inns, Jeehwan Kim, Davendra k. Sadana, Katherine L. Saenger
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Patent number: 8298923Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.Type: GrantFiled: October 27, 2010Date of Patent: October 30, 2012Assignee: International Business Machinces CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, Katherine L. Saenger
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Publication number: 20120104390Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, Katherine L. Saenger
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Publication number: 20120031476Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers.Type: ApplicationFiled: August 4, 2010Publication date: February 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Harold J. Hovel, Daniel A. Inns, Jee H. Kim, Alexander Reznicek, Devendra K. Sadana
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Publication number: 20110162702Abstract: A method of texturing a surface of a substrate utilizing a phase-segregated mask and etching is disclosed. The resulting textured surface, which can be used as a component of a solar cell includes, in one embodiment, a randomly mixed collection of flat-topped and angled surfaces providing local high points and local low points. The flat-topped surfaces have an areal density of at least 1%, and the high points are coincident with the flat-topped surfaces. Moreover, a preponderance of said low points are approximately situated in a single common plane parallel to the plane defined by the flat-topped surfaces.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roy A. Carruthers, Keith E. Fogel, Daniel A. Inns, Katherine L. Saenger
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Patent number: 7914619Abstract: The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 ?m to 40 ?m on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.Type: GrantFiled: November 3, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Daniel A. Inns, Devendra K. Sadana, Katherine L. Saenger
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Publication number: 20100221867Abstract: A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.Type: ApplicationFiled: May 6, 2009Publication date: September 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Harold J. Hovel, Daniel A. Inns, Jeehwan Kim, Devendra K. Sadana, Katherine L. Saenger, Ghavam G. Shahidi
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Patent number: 7749869Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.Type: GrantFiled: August 5, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Joel P. De Souza, Harold John Hovel, Daniel A. Inns, Devendra K. Sadana, Ghavam G. Shahidi
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Publication number: 20100112792Abstract: The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 ?m to 40 ?m on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.Type: ApplicationFiled: November 3, 2008Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Daniel A. Inns, Devendra K. Sadana, Katherine L. Saenger
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Publication number: 20100035409Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.Type: ApplicationFiled: August 5, 2008Publication date: February 11, 2010Inventors: Joel P De Souza, Harold John Hovel, Daniel A. Inns, Devendra K. Sadana, Ghavam G. Shahidi
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Publication number: 20080276986Abstract: A photolithography method for contacting one or more contact regions of a thin-film semiconductor structure on a transparent supporting material is disclosed. The method comprises the steps of forming one or more openings (6a) in the semiconductor structure (2, 3, 4) to substantially expose respective surface portions (5a) of the supporting material (5) and respective contact regions (4a); covering the surface of the semiconductor structure with a positive photoresist (7); illuminating the semiconductor structure with an exposing light through the supporting material such that first portions of the photoresist covering the substantially exposed surface portions of the supporting material and at least portions of the contact regions respectively are exposed to the exposing light and such that the exposing light is absorbed in the semiconductor structure, leaving one or more second portions of the photoresist covering the semiconductor structure unexposed.Type: ApplicationFiled: February 28, 2006Publication date: November 13, 2008Applicant: NEWSOUTH INNOVATIONS PTY LIMITEDInventors: Armin Gerhard Aberle, Timothy Michael Walsh, Daniel A. Inns