Abstract: An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.

Abstract: An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.

Abstract: The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ.

Abstract: An apparatus and method is provided for reducing the area of integrated circuits using cells with multiple unrelated gates. A netlist is generated which includes cells and interconnecting nets. Each cell represents a circuit and each net represents an interconnection between cells. Combinable cells of the netlist are paired to create a list. A combinable cell represents a circuit having at least one transistor formed on a substrate area. This transistor includes a diffusion layer directly coupled to a voltage source via a diffusion contact, wherein the diffusion contact is positioned adjacent an outer edge of the substrate area. A combinability score is calculated for each pair of combinable cells of the list. Each combinability score is calculated as a function of the number of nets representing direct or indirect interconnections between a pair of combinable cells. The pair of combinable cells corresponding to the highest combinability score is removed from the netlist. Thereafter, a combined cell is added.