Abstract: A system for configuring user-defined recognition patterns at an edge device using a hybrid cloud-edge device approach has a pattern recognition integrated circuit implementing a machine learning pattern recognizer that generates an event recognition output in response to an input thereto based upon pre-trained machine learning weights stored in a memory of the pattern recognition integrated circuit. A remote pattern recognition training service is in communication with a secondary user device receptive to a training input of the user-defined recognition patterns, and returns a set of training weights corresponding to the training input. An application interface connects the pattern recognition integrated circuit to the secondary user device, with the set of training weights returned to the secondary user device being transferable to the machine learning pattern recognizer for storage in the memory of the pattern recognition integrated circuit.

Abstract: A configurable monitoring and actioning system has one or more programmable edge devices each including a machine learning pattern recognizer, a sensor providing sensor input data to the pattern recognizer, and a memory storing pre-trained machine learning weight values for the pattern recognizer. Event detections are generated based upon evaluations of the sensor input data from the sensor against the pre-trained machine learning weight values. An application installable on a user device is in communication with each of the one or more programmable edge devices and executes predetermined actions based upon the event detection evaluations from the machine learning pattern recognizer.

Abstract: An always-on local action controller has one or more sensors each receptive to an external input. The respective external inputs are translatable to corresponding signals. One or more always-on data analytic neural network subsystems are each connected to a respective one of the sensors and are receptive to the signals outputted therefrom. An event detection is raised by a given one of the always-on data analytical neural network subsystems in response to a pattern of signal data corresponding to an event. A decision combiner is connected to each of the one or more always-on data analytic neural network subsystems, which generates an action signal based upon an aggregate of the events.

Abstract: A deep learning training and inference system for a primary machine learning system has an automated data collection tool receptive to incoming input data from a sensor data source, and embeds one or more sensor data classifications associated with the incoming input data. A data augmentation tool is receptive to the input data from the automated data collection tool and generates an augmented input data set resulting from one or more predefined operations applied to the input data. An adaptive training tool is receptive to the augmented input data set to improve performance, with a new set of weight values being generated for the primary machine learning system. An inference tool is in communication with the adaptive training tool to receive the new set of weight values for an inference model simulator emulating a native hardware environment of the primary machine learning system.

Abstract: A device wake-up system has one or more sensors each receptive to an external input. The respective external inputs are translatable to corresponding signals. One or more feature extractors connected to a respective one of the one or more sensors are receptive to the signals outputted from the sensors, and the feature data is associated with the signals being generated by the corresponding one of the one or more feature extractors. One or more inference circuits are connected to a respective one of the one or more feature extractors, and inference decisions are generated from patterns of the feature data generated by a corresponding one of the one or more feature extractors. A decision combiner is connected to each of the one or more inference circuits, and a wake signal is be generated based upon an aggregate of the inference decisions provided by the one or more inference circuits.

Abstract: A voice-activated system edge device cooperating with a remote command processor has a state machine defined by a listening mode state and a conversation monitoring mode state. The state machine transitions from the listening mode state to the conversation monitoring mode state in response to a wake word detection. A command accompanying the wake word is transmitted to the remote command processor for execution thereon. The conversation monitoring mode state is maintained for a conversation monitoring window time duration to receive a connection word accompanied by another command transmitted to the remote command processor for further execution thereon.

Abstract: A neural network parameter tuner has an auxiliary neural network receptive to an input data stream with signal components and noise components associated with ambient conditions. An ambient classification value is periodically derived from the input data stream based upon the noise components detected therein. A primary neural network receptive to the input data stream classifies the input data stream based upon an assigned detection threshold corresponding to the ambient classification value.

Abstract: A multi-stage selectable neural network noise suppression system has a first stage noise pattern selection neural network receptive to an input signal. An automatic noise classification is generated based upon an evaluation of the input signal. A noise suppression weight table stores one or more sets of automatic noise suppression weight values corresponding to the generated automatic noise classifications. A second stage noise pattern suppression neural network then selectively applies a specific automatic targeted noise suppression based upon the automatic noise suppression weight values. This approach balances performance quality and power/memory usage that efficiently tailors noise detection and suppression.

Abstract: A system monitors vibration activity in a press machine environment and generates a signal indicative of vibration level severity. An accelerometer can provide measured peak acceleration data that serves as an indication of vibration level. The vibration measurement, is compared to a reference vibration level that corresponds to a run condition of desired operating parameters. A controller controls the press machine shutheight in accordance with the differential expressed in the comparison result. The consequent shutheight adjustment effects a change in the vibration activity that acts as a correction to the deviation in vibration behavior expressed by the differential.

Abstract: A system monitors vibration activity in a press machine environment and generates a signal indicative of vibration level severity. An accelerometer can provide measured peak acceleration data that serves as an indication of vibration level. The vibration measurement, is compared to a reference vibration level that corresponds to a run condition of desired operating parameters. A controller controls the press machine shutheight in accordance with the differential expressed in the comparison result. The consequent shutheight adjustment effects a change in the vibration activity that acts as a correction to the deviation in vibration behavior expressed by the differential.

Abstract: A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a Pseudo Random Bit Stream (PRBS) function. The input ordering block is operates to receive a first plurality of transmit bit streams at a first bit rate, order the first plurality of transmit bit streams based upon a first order select signal, and produce a first plurality of ordered transmit bit streams at the first bit rate. The input ordering block may also deskew the first plurality of transmit bit streams. The plurality of multiplexers operate to receive the first plurality of ordered transmit bit streams at the first bit rate and produce an interface plurality of transmit bit streams at an interface bit rate. The output ordering block operates to order the interface plurality of transmit bit streams based upon an interface order select signal. The PRBS function produces a PRBS that is coupled to at least one of the interface plurality of transmit bit streams.

Abstract: A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits.

Abstract: A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: Multiple ICs communicate with a controller through a shared bus. The ICs are also joined to an output of the controller in a daisy chain configuration. Each IC includes an input for receiving a signal on a link of the daisy chain and an output for providing a signal on a link of the daisy chain. The daisy chain links are used for address initialization. Thus only one controller pin and two IC pins are required for address initialization. The daisy chain links may be used for distributing address data, or may be used for distributing an enable signal that allows an IC to store address data provided on the shared bus.

Abstract: A die monitoring system for use in a press machine includes a die element, a vibration severity monitor, and a monitor receiving portion. The vibration severity monitor is configured for monitoring a vibration severity condition of the die element. The monitor receiving portion is associated with the die element and includes a monitor cavity. This monitor cavity is configured for an operable mounting of the vibration severity monitor therewithin. A primary feature of the vibration severity monitor is that it can remain with a particular die throughout the lifetime thereof, even if the die is interchanged between machine presses.