Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract: L-shaped spacers for use adjacent to the vertical sidewalls of gate electrodes in the manufacture of MOS integrated circuits are described along with methods of fabricating such structures that do not require any additional cost compared to conventional manufacturing processes. A spacer is formed as a tri-layer of silicon oxide/silicon nitride/silicon oxide deposited in- situ at low temperature using a conventional furnace and a bis(tertiarybutylamino) silane chemistry deposition. The spacer has the same performance as a conventional spacer during deep source/drain (S/D) implants. Prior to a cleaning operation which precedes silicidation, the top oxide layer is removed leading to improved gap-fill characteristics. The upper oxide may to removed before deep S/D implantation to further achieve reduction of series resistance.

Abstract: A method and apparatus for performing per-port Internet Protocol (IP) multicast pruning, proxying of IP multicast group membership reports, and generating pseudo membership queries for determining IP multicast group membership are provided. A switch may implement per-port IP multicast pruning by establishing a mapping of IP multicast groups to its ports. The mapping is based upon membership reports received from each end-station participating in an IP multicast group. Based upon the mapping, the switch forwards IP multicast packets only to those of the end-stations that are participating in the IP multicast group addressed. Once per-port IP multicast pruning is implemented, multicast routers must process membership reports from all end-stations participating in an IP multicast group. To reduce this burden, a switch may act as a proxy device. The switch receives a membership report identifying an IP multicast group.

Abstract: A method of configuring a network. The network includes some physical devices, some hosts, and a network management tool. The method comprises the following steps. First, generate a set of leaf nodes. Each leaf node includes at least one physical device and connects to at least one host. Next, generate an adjacency matrix from said set of leaf nodes. Next, generate a set of interconnect nodes, the interconnect nodes connect the set of leaf nodes. Next, determine the resource availability for the set of interconnect nodes. Finally, configure the set of interconnect nodes and the set of leaf nodes after determining that sufficient resources are available.

Abstract: An improved complex bandpass digital filter is disclosed. According to the invention, a complex bandpass digital filter having symmetric complex coefficients is implemented using a ROM look-up table. In operation, an input bit stream is latched at a desired decimation rate and the resulting latched bits are then used to address a ROM according to the following two-cycle process: First, the bits are applied in nomal order to the ROM to obtain the real (in phase) portion of the filter output. Second, the bits are bit-reversed and then applied to the same ROM to obtain the imaginary (quadrature) portion of the filter output. Thus, complex outputs are obtained as a time-multiplexed stream from one ROM, resulting in reduced ROM storage capacity requirements.

Abstract: Disclosed is a digital zero-IF selectivity section circuit which operates on a recovered input signal, digitally clocked by a first clock at a rate of FS, in receiver device. The circuit uses a second clock operating at a lesser rate than the first clock to clock an N-order FIR digital filtering means to selectively band-limit the frequency spectrum of the recovered input signal. A second digital filtering means is coupled to the output of the first FIR digital filtering means. The second digital filtering means operates at a clock speed less than or equal to the second clock speed. The second digital filtering means is used to further selectively band-limit the frequency spectrum of the recovered input signal.