Abstract: Various embodiments relate to detecting loss of electrical energy. A method of detecting loss of electrical energy may include determining, for a number of time samples, a neutral current and an imputed neutral current of an electrical energy metering system. Further, the method may include determining, for each of the number of time samples, a squared difference between the neutral current and the imputed neutral current. The method may further include detecting, based on the squared difference, loss of electrical energy from the electrical energy metering system.

Abstract: Various embodiments relate to detecting loss of electrical energy. A method of detecting loss of electrical energy may include determining, for a number of time samples, a neutral current and an imputed neutral current of an electrical energy metering system. Further, the method may include determining, for each of the number of time samples, a squared difference between the neutral current and the imputed neutral current. The method may further include detecting, based on the squared difference, loss of electrical energy from the electrical energy metering system.

Abstract: Various embodiments relate to detecting theft of electrical energy. A method of detecting theft of electrical energy may include measuring, for each time sample of a number of time samples, a neutral current of an electrical energy metering system. The method may further include summing, for each time sample of the number of time samples, a number of measured phase current values of the electrical energy metering system to determine an imputed neutral current. Further, the method may include determining, for each time sample of the number of time samples, a squared difference between the measured neutral current and the imputed neutral current. Moreover, the method may include integrating, for each time sample of the number of time samples, the squared difference to determine an accumulator value. In addition, the method may include detecting, based on the accumulator value, theft of electrical energy from the electrical energy metering system.

Abstract: Various embodiments relate to detecting theft of electrical energy. A method of detecting theft of electrical energy may include measuring, for each time sample of a number of time samples, a neutral current of an electrical energy metering system. The method may further include summing, for each time sample of the number of time samples, a number of measured phase current values of the electrical energy metering system to determine an imputed neutral current. Further, the method may include determining, for each time sample of the number of time samples, a squared difference between the measured neutral current and the imputed neutral current. Moreover, the method may include integrating, for each time sample of the number of time samples, the squared difference to determine an accumulator value. In addition, the method may include detecting, based on the accumulator value, theft of electrical energy from the electrical energy metering system.

Abstract: A circuit and method for determining connection status of a phone line shared by multiple telecommunications devices, such as modems and phones, are provided. The phone line includes respective tip and ring lines. The circuit comprises a first operational amplifier coupled to receive a signal indicative of a voltage difference between the respective tip and ring lines. The circuit further comprises a lag network coupled to impart a predetermined delay to the output signal from the first operational amplifier. A second operational amplifier is coupled to receive the voltage difference signal. The output signal from the second operational amplifier has a sufficiently fast time response relative to the output signal from the lag network.

Abstract: A circuit for determining connection status of a phone line shared by multiple telecommunications devices, such as modems and phones, is provided. The phone line includes respective tip and ring lines. The circuit comprises a first transistor stage coupled to receive a signal indicative of a voltage difference between the respective tip and ring lines. The first transistor stage is configured to supply an output signal having a predetermined time response. The circuit further comprises a second transistor stage coupled to the first transistor stage and configured to supply an output signal having a slow time response relative to the output signal from the first transistor stage.

Abstract: Line voltage and line current signals are sensed on a power line having at least one conducting path. The sensed line voltages and line currents are converted into a digital signal. A phase-to-neutral voltage signal and phase current signal are computed from the digital signal to thereby define a phase of the power line. An interval of orthogonality is determined from the sensed voltage and current signals, coinciding with passage of an integral number of cycles of a fundamental frequency reference signal which is computed from the computed phase-to-neutral voltage signal. A vector metering quantity is computed for the determined interval of orthogonality from the computed phase-to-neutral voltage signal and the computed phase current signal. The vector metering quantities to be computed may be identified and computed based upon an associated detent. The vector metering quantity is also computed based on an identified circuit topology.

Abstract: Line voltage and line current signals are sensed on a power line having at least one conducting path. The sensed line voltages and line currents are converted into a digital signal. A phase-to-neutral voltage signal and phase current signal are computed from the digital signal to thereby define a phase of the power line. An interval of orthogonality is determined from the sensed voltage and current signals, coinciding with passage of an integral number of cycles of a fundamental frequency reference signal which is computed from the computed phase-to-neutral voltage signal. A vector metering quantity is computed for the determined interval of orthogonality from the computed phase-to-neutral voltage signal and the computed phase current signal. The vector metering quantities to be computed may be identified and computed based upon an associated detent. The vector metering quantity is also computed based on an identified circuit topology.

Abstract: Line voltage and line current signals are sensed on a power line having at least one conducting path. The sensed line voltages and line currents are converted into a digital signal. A phase-to-neutral voltage signal and phase current signal are computed from the digital signal to thereby define a phase of the power line. An interval of orthogonality is determined from the sensed voltage and current signals, coinciding with passage of an integral number of cycles of a fundamental frequency reference signal which is computed from the computed phase-to-neutral voltage signal. A vector metering quantity is computed for the determined interval of orthogonality from the computed phase-to-neutral voltage signal and the computed phase current signal. The vector metering quantities to be computed may be identified and computed based upon an associated detent. The vector metering quantity is also computed based on an identified circuit topology.

Abstract: A field-testable integrated circuit that includes a plurality of analog signal channels for receiving a respective analog signal during a normal mode of operation is provided. Individual test circuits are built-in within the integrated circuit for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels. Each test circuit includes a channel decoder responsive to predetermined channel select signals for producing a respective channel decoder output signal. A multiplexer is responsive to predetermined reference select signals and to the decoder output signal for supplying during the test mode of operation a selected one of the predetermined reference signals to the respective analog channel being coupled to the individual test circuit therein.

Abstract: A current sensor has one signal interface channel including a transformer having a primary winding, a secondary winding and a feedback winding. A magnetic core magnetically couples the primary winding, the secondary winding and the feedback winding. The current sensor further includes a feedback generating circuit responsive to an AC signal in the secondary winding for generating a feedback signal having a continuous polarity supplied to the feedback winding. The feedback signal being effective for maintaining a flux in the magnetic core substantially near zero. The feedback generating circuit is made up of an operational amplifier, such as an amplifier having first and second differential input ports and first and second differential output ports, and a switching assembly designed to generate a compensating AC signal from a DC offset voltage. The compensating AC signal is conveniently coupled to the operational amplifier through the magnetic core.

Abstract: A decimation filter for filtering an externally derived stream of quantized electrical signals having a predetermined rate includes a coefficient generator responsive to a set of externally derived decimation-ratio select signals to provide a separate normalized coefficient signal at each respective one of a plurality of output ports. An accumulator is coupled to the coefficient generator to receive each normalized coefficient signal generated therein. The accumulator receives the stream of quantized electrical signals so as to produce, upon masking with respective ones of the received normalized coefficient signals, a plurality of accumulator output signals. An overflow detector is coupled to the accumulator to detect and correct any overflow condition arising in the accumulator.

Abstract: A decimation filter for filtering an externally derived stream of quantized electrical signals includes a coefficient generator responsive to a set of externally derived decimation-ratio select signals to provide a separate normalized coefficient signal at each respective one of a plurality of output ports. The coefficient generator employs a zero-fill circuit comprising first and second circuits which selectively ripple therethrough an scaling-control output signal from a demultiplexer unit in order to provide the normalized coefficient signals. An accumulator is coupled to the coefficient generator to receive each normalized coefficient signal generated therein. The accumulator receives the stream of quantized electrical signals so as to produce, upon masking with respective ones of the received normalized coefficient signals, a plurality of accumulator output signals. An overflow detector is coupled to the accumulator to detect and correct any overflow condition arising in the accumulator.

Abstract: A decimation circuit for filtering a stream of quantized electrical signals while providing phase angle correction and a substantially linear phase response over a predetermined passband range F.sub.B is provided. The stream of quantized electrical signals arrives at a predetermined rate F.sub.M from an oversampling delta-sigma modulator. The decimation circuit includes a decimation filter for filtering the stream of quantized electrical signals to provide a filtered output signal at an output ram F'.sub.S defined by F'.sub.S =F.sub.M /R wherein R is a positive integer. A phase corrector is coupled to the decimation filter to receive the filtered output signal and to correct the phase angle of the received filtered signal so as to provide an equalized phase angle at least over the predetermined range F.sub.B. The value for R is selected such that output rate F'.sub.S is sufficiently situated above bandpass range F.sub.

Abstract: A decimation circuit for filtering a stream of quantized electrical signals while providing a substantially uniform magnitude and a substantially linear phase response over a predetermined passband range F.sub.B is provided. The stream of quantized electrical signals arrives at a predetermined rate F.sub.M from an oversampling delta-sigma modulator. The decimation circuit includes a decimation filter for filtering the stream of quantized electrical signals to provide a filtered output signal at an output rate F.sub.S. The decimation filter has a frequency response defined by ##EQU1## wherein k is a positive integer, T is the sampling period of the decimation filter and R is a decimation ratio defined by R=F.sub.M /F.sub.S. A magnitude corrector is coupled to the decimation filter to receive the filtered output signal and to correct the magnitude of the received filtered signal at least over the predetermined range F.sub.B. The decimation ratio is selected such that output rate F.sub.

Abstract: Serial memories are operated so as to reorder samples as they are serially supplied in a pipelined electronics system, such as one for performing matrix multiplications on a chain serial basis. A serial memory comprising (m-1) delay elements and a write multiplexer is operated so as to respond to data samples that occur every m.sup.th one of a series of consecutive sample intervals to generate successive groups of m successive samples, for example. As a further example, a serial memory comprising (mn-1) delay elements and a write multiplexer is operated so as to respond to every m.sup.th one of data samples supplied thereto, which said every m.sup.th data sample is in a first scanning order, to supply those every m.sup.th data samples in a second scanning order. The first scanning order may correspond to scanning in row major order a matrix of samples arranged in m rows and n columns, in which case the second scanning order corresponds to column major scanning order of that matrix of samples.

Abstract: A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.

Abstract: Digital electronic apparatus for performing chain-serial matrix multiplications using a single pipeline multiplier supplies elements of the multiplicand and multiplier matrices to the digital memory from first and second memories. Each product matrix is temporarily stored in a third memory until such time as it is used to write the first memory for the next matrix multiplication in the series. This procedure avoids overwriting the first memory when its data are still required for application to the pipeline multiplier.

Abstract: An inertial transformation matrix generator generates a succession of Euler transformation matrices in inertial coordinates, and is useful for converting to inertial coordinates the responses of a sensor hard mounted on the hull of a craft (e.g., an aircraft). First, second and third rate-sensing gyros located proximately to said sensor are strapped down to the craft hull, and are oriented to sense the motion of the craft hull in three mutually orthogonal directions, for providing respective output signals indicative of components of craft hull motion in each of those three mutually orthogonal directions. The output signals of the gyros are digitized, and based on these digital signals successive incremental Euler transformation matrices are generated.

Abstract: A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.