Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.

Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.