Abstract: System and method for partitioning a DSLAM network. In this regard, one such network can be broadly summarized by a representative communication system comprising a digital subscriber line access multiplexer (DSLAM) that is communicatively coupled on its line-side to a high-speed digital link. The DSLAM is communicatively coupled through the high-speed digital link with the trunk side of a remote line access unit (RLAU). The RLAU is communicatively coupled on its line-side to a first digital subscriber line (DSL).

Abstract: A system and method for ATM header compression for DSL links is provided. One embodiment, among others, for compressing ATM headers for communication across an ATM network involves transmitting an initial full ATM header to a receiver in the ATM network. Thereafter, when data payloads are available for transmission, the ATM header that corresponds to the data payload is compressed by either a differential technique, dictionary technique, or a multi-cell technique. The compressed ATM header and the data payload are then communicated over the ATM network to the receiver, wherein the receiver is enabled to interpret the compressed ATM header accordingly. By compressing the ATM header, a greater number of ATM cells may be communicated in the ATM network than if the ATM header were communicated in an uncompressed format.

Abstract: A method and apparatus are disclosed for reducing crosstalk in a telecommunication system. Broadly, the present invention utilizes a common mode signal to obtain additional information that can be used to better approximate the transmitted signal (by approximating and canceling crosstalk or otherwise). In accordance with one embodiment of the invention, a modem is provided having improved crosstalk cancellation circuitry for canceling crosstalk received on a local loop (or otherwise estimating the remotely transmitted signal) carrying modem communications. The modem includes a first input for receiving a signal carried on the local loop and a second input for receiving a signal obtained from the common mode. The modem further includes processing circuitry configured to either reduce crosstalk present in the signal carried on the local loop, or to otherwise closely approximate the remotely transmitted signal.

Abstract: An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by triggering a counter to supply a count responsive to a higher-frequency replica of the local clock signal with the network clock signal. A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and or further manipulated to generate a phase error correction signal for use in a clock synchronization control loop.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase without increasing the maximum current in the line driver output stage. The output stage of the line driver may comprise a first amplifier, a second amplifier, and an integrated back-matching resistor network. In order to further increase the available transmit power; a protective semiconductor device may be added to a line driver output stage for each semiconductor device in the first and second amplifiers. A third embodiment of a line driver output stage in accordance with the present invention may comprise a combination of the integrated back-matching resistor network along with the protective semiconductor devices.

Abstract: The present invention is directed to a system and method that detects periods of no activity in the downstream data path of a DSL modem and reduces the transmit power in the output line driver to reduce power consumption in the modem. A preferred method is operative at the central office DSL modem and comprises detecting periods of no activity in the downstream data bins, reducing the transmit power in response to the inactivity on the communication link, detecting either upstream or downstream data, and performing a fast retrain of the modem to restore nominal power data transmission in the downstream direction. A variation of the preferred method uses a reduced point constellation encoding scheme to reduce power consumption. Broadly, the system of the present invention may be realized by a configurable transmit channel line driver and a digital signal processor.

Abstract: A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: A system and method for performing peak-to-average power ratio reduction in a transmitter using pulse amplitude modulation (PAM) encoding. Broadly, a transmitter is configured to perform active digital filtering to detect encoded data symbols that if uncorrected would lead to relatively high analog signal peaks in the data transmission. A prediction is made of the peak values that would be applied at the digital to analog converter (DAC) if the original output of the Tomlinson precoder was sent into the shaping filter. If the absolute value of the predicted peak value exceeds a threshold, a correction of a full 2L step is applied for one sample of the Tomlinson precoded stream. The correction step is applied in such a way as to reduce the resulting peak output. Two methods of predicting the peak values are presented. The first method segments the shaping filter into causal and non causal portions so that no extra delay is introduced.

Abstract: The present invention is directed to a system and method for reducing the need to perform signal clipping in a DMT transmitter. In accordance with one aspect of the invention, a method performs an inverse Fourier Transform on the input to produce a time-domain, digital value to be transmitted to a remote receiver. The method then evaluates the magnitude of the digital value to determine whether the magnitude exceeds a threshold value. Then, the method alters the input and re-performs an inverse Fourier Transform on the altered input, only if the step of evaluating the magnitude determines that the magnitude of the digital value exceeds the threshold value.

Abstract: An ADSL system for operating in a time duplex system that provides alternative configurations for limiting crosstalk in a broadband network is disclosed. The ADSL system introduces a trial bitmap profile configuration to maximize the bit rate at which information is transmitted, regardless of network topology. In a simplified embodiment, a composite signal to noise ratio is derived from a minimum far end crosstalk signal to noise ratio and a minimum near end crosstalk signal to noise ratio. A maximum bit rate for the transfer of information, which is directly related to the derived composite SNR, is then determined. Information is then transmitted simultaneously between an asymmetric digital subscriber line central office and an asymmetric digital subscriber line customer premise at the determined maximum bit rate.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that excessive reads to and writes from memory consume excessive amounts of power. Accordingly, the circuit of the present is specifically designed to minimize the number of reads and writes to memory. In addition, the circuit is designed so that processing parallelism may be achieved in order to reduce the total number of clock cycles required to compute a FFT. In accordance with one aspect of the invention, the processing circuit includes a data memory for storing data values, and a separate coefficient memory for storing coefficient (or twiddle) values. The circuit further includes a multiplier configured to multiply values received from the coefficient memory and another value retrieved from some other location.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase by limiting the output stage signal path to NMOS and NPN bipolar semiconductor devices. The output stage of the improved line driver may comprise a first amplifier, a second amplifier, a first transformer, a second transformer, and a plurality of back-matching resistor networks. A second embodiment of an improved output stage of a line driver may comprise a first amplifier, a second amplifier, a transformer, and a plurality of back-matching resistor networks. Both preferred embodiments may be implemented with CMOS and bipolar semiconductor devices, as well as, a combination of the two semiconductor technologies.

Abstract: A system and method for characterizing a transmission line in a digital subscriber line (DSL) system. Broadly, the method uses DSL system components, which are configured to perform time domain reflectometry (TDR), in order to determine transmission line characteristics.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that memory space for the storage of symmetrical coefficients can be realized by storing the coefficients associated with one complex number in order to generate eight related complex numbers. Accordingly, the circuit of the present invention is specifically designed to minimize the coefficient memory requirements for symmetrical coefficients.

Abstract: A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: The present invention entails a programmable data communications protocol conversion unit (PCU) and method. The PCU is a processor circuit which includes a means for performing full parallel, partial parallel, and bit data transfers. In particular, a bit assembly register is employed to assemble partial parallel data blocks which comprise data with a number of bits that is less than the order of the data bus of the PCU. The bit assembly register further includes the capability of writing the partial parallel data block to predetermined locations using a full parallel transfer and a shadow bus with bits indicating the validity of the particular bits in the data block transferred. The particular circuits receiving partial parallel writes include a register for receiving data and a register for receiving the corresponding shadow bits. Invalid data written to these registers is ignored while valid data is shifted accordingly, for example, out to a serial interface.

Abstract: The present invention is directed to an improved direct memory access controller, having built-in arbitration circuitry, whereby multiple, identical, DMA controllers may be cascaded within a computing system, without requiring additional (i.e., separate) arbitration circuitry. In accordance with one aspect of this invention, a DMA controller is provided having a first input for connection to a DMA Acknowledge signal, and a first output for connection to a DMA Request. A second output is also provided for carrying a signal that is representative of activity of the DMA controller. In this regard, the second output may be configured to output a signal in either an Enable state or Inhibit state. If the DMA controller is active (i.e., presently controlling the transfer update among memory devices), then the second output is placed in an Inhibit state. Otherwise, the second output is controlled to be in an Enabled state.

Abstract: Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase without increasing the maximum current in the line driver output stage. The output stage of the line driver may comprise a first amplifier, a second amplifier, and an integrated back-matching resistor network. In order to further increase the available transmit power; a protective semiconductor device may be added to a line driver output stage for each semiconductor device in the first and second amplifiers. A third embodiment of a line driver output stage in accordance with the present invention may comprise a combination of the integrated back-matching resistor network along with the protective semiconductor devices.

Abstract: In general, the multi-mode analog front-end provides an internal line driver and hybrid, as well as numerous functions, in order to provide a close to optimum solution for all digital subscriber line applications. The functions provided for by the analog front-end include; programmable hybrid attenuation; onboard amplifiers for driving external transmit and receive filters; a line driver with programmable drive and gain; programmable RC-filters capable of calibration via an internal loop-back under digital control; a programmable switched-capacitor filter for tracking the over sampling rate used by a digital signal processor; internal testing functions; a high frequency boost circuit; a dual input peak detector; selectable data rates; and a programmable data interface. The analog front-end allows for use of particular blocks within the analog front-end particular to the functions necessary to compensate for a particular digital subscriber line application.