Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.

Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.

Abstract: A device including a NAND-flash memory comprising a read-only portion storing boot code and a key, and a system on a chip (SoC) coupled to the NAND-flash memory is provided. The SoC includes a read-only memory (ROM) storing one or more instructions and a processor configured to execute, upon startup, the one or more instructions stored in the ROM to request from the NAND-flash memory the boot code and the key. The processor further configured to load and execute the boot code to perform a chain of trust verification process on subsequent code during a booting process using the key. A method for using the device is also presented.

Abstract: A device including a NAND-flash memory comprising a read-only portion storing boot code and a key, and a system on a chip (SoC) coupled to the NAND-flash memory is provided. The SoC includes a read-only memory (ROM) storing one or more instructions and a processor configured to execute, upon startup, the one or more instructions stored in the ROM to request from the NAND-flash memory the boot code and the key. The processor further configured to load and execute the boot code to perform a chain of trust verification process on subsequent code during a booting process using the key. A method for using the device is also presented.

Abstract: A non-transitory computer-readable storage medium may include instructions stored thereon. When executed by at least one processor, the instructions may be configured to cause a computing system to at least maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application, and grant the instruction direct access to memory, bypassing an operating system running on the computer, based on the count of memory misses meeting or exceeding a threshold.

Abstract: A method includes determining which of a plurality of blocks of data in a data storage device having a plurality of memory devices to copy during garbage collection using a cost function based on a number of free pages and a number of replicated pages in each of the blocks, where the replicated pages include replicated data that is a copy of data stored in another storage device and determining not to copy one or more of the blocks of data during garbage collection based on the cost function.