Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

Abstract: Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.