Abstract: An asymmetric-rate communication method and system for remote data collection using a processor-operated modem at a respective data collection site is provided. The modem processor used at the data collection site may be rated to have a predetermined relatively low processing power. The method includes a first selecting step that allow for selecting a first protocol for transmitting data at a predetermined rate. The selected first protocol uses a predetermined percentage of the processing power of the processor. The method includes a second selecting step that allows for selecting a second protocol for receiving data at another predetermined rate. The selected second protocol uses another predetermined percentage of the processing power of the processor.

Abstract: An on-chip watchdog circuit is provided that generates an output signal when an error signal generated by a circuit under test is detected. The on-chip watchdog circuit comprises a logic gate that is connected to a clock signal and receives a signal in response to the error signal generated by the circuit under test. A gate output circuit is connected to an output of the logic gate. An RC circuit is connected to the gate output circuit. A voltage divider is connected to the RC circuit. A comparator is connected to the voltage divider and provides the output signal in response to the error signal generated by the circuit under test, and the on-chip watchdog circuit and the circuit under test are integrated on a same semiconductor microchip.

Abstract: A current sensor assembly includes a plurality of symmetric current conductors that pass asymmetrically through an opening in a toroidal core having a sensing winding wound on the core. A blade is connected to each end of the conductors. Each of the conductors has the general shape of a “V” as viewed along a central axis passing through the opening in the toroidal core.

Abstract: A current sensor assembly includes a plurality of symmetric current conductors that pass asymmetrically through the sensor assembly. A blade is connected to each end of the conductors. The conductors have a diagonal symmetry and have the general shape of a “V” as viewed from the top of the sensor assembly. The conductors pass through an opening located at the center of the current sensor.

Abstract: In accordance with one embodiment of the present invention, a method of forming a toroidal winding assembly comprises: forming a longitudinal assembly having a first assembly end and a second assembly end; bending the longitudinal assembly to form a generally toroidal assembly; and bonding the first assembly end to the second assembly end to form the toroidal winding assembly.

Abstract: A low cost and easy to assemble communicating utility meter provides selectable measurement, calibration, display, and communications means so as to be re-configurable based on several factors including; harmonic content of the power signal measured, LCD display alternatives, time of use measurements, bandpass filter settings, power quality measurements, PLC communications alternatives, radio frequency communications alternatives, optical communications alternatives, and hard wire communications alternatives.

Abstract: A low cost and easy to assemble communicating utility meter provides selectable measurement, calibration, display, and communications means so as to be re-configurable based on several factors including; harmonic content of the power signal measured, LCD display alternatives, time of use measurements, bandpass filter settings, power quality measurements, PLC communications alternatives, radio frequency communications alternatives, optical communications alternatives, and hard wire communications alternatives.

Abstract: A low cost mixed analog digital application specific integrated circuit (ASIC) includes a standard central processing it (CPU) programmed to execute a correlation function for arc detection. Use of a standard CPU is possible because need for digital fourier analysis is eliminated by the ASIC architecture. The SIC includes a power supply configured to be coupled to an AC power line for supplying power to the ASIC components, and further includes a current sensor coupled to a current-carrying conductor for generating a signal representative of current in the conductor. A first analog-to-digital converter (ADC), coupled in series with the current sensor, has its output coupled to a central processing unit (CPU). The CPU supplies a digital-to-analog converter (DAC) with a digital signal representative of a portion of the sensed current. The DAC supplies this signal, in analog form, to a summer, which also receives an output signal from the current sensor.

Abstract: A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system, such as delta-sigma modulators and decimation filters having a selectable decimation ratio, allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system.

Abstract: A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system.