Patents by Inventor Daniel Aubertine

Daniel Aubertine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9614060
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Publication number: 20160284821
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Patent number: 9385221
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Publication number: 20150221744
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Patent number: 9064944
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Publication number: 20140264280
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Patent number: 7663192
    Abstract: A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Anand Murthy, Mark Liu, Daniel Aubertine