Abstract: Common mode error correction for differential amplifiers involves accurately measuring both the input and output of an amplifier using a low-leakage measurement path, and calculating common-mode gain. Two measurements are made at each node by appying two different common-mode voltages. Subtracting one set of measurements from the other eliminates voltage offset errors, and leaves a common-mode error term for gain calculation. The common-mode gain factor is stored, and thereafter, common mode error may be subtracted from measurements made by the differential amplifier.

Abstract: A voltage and resistance synthesizer includes a pulse width modulator (PWM) for synthesizing voltage and resistance values at a pair of terminals. A selector switch selects between a resistance synthesis mode, in which resistance values are synthesized from a single reference resistor, and a voltage synthesis mode, in which voltage values are synthesized from a single reference voltage. The pulse width modulator permits digital control words to be received which govern the synthesized value with 16 bit resolution. A low pass filter blocks the switching frequency components and provides a d.c. voltage which is the product of the duty cycle and the reference value.

Abstract: A low impedance overvoltage protection circuit includes a first MOSFET having a drain connected to an input signal and a source connected to a drain of a second MOSFET, the source of the second MOSFET being coupled to the output. The gates of the first and second MOSFETs are connected to voltage supplies which float relative to the input signal values so as to maintain the gates of the respective MOSFETs biased to a conducting state. The maximum and minimum values to which the floating voltage supplies will float are defined by clamping diodes and clamp voltage sources. When the input signal value exceeds a desired positive maximum value, the first MOSFET is no longer biased to an on state whereby the MOSFET turns off, shunting the input signal through a high impedance for limiting input current and removing the input signal from the output. Negative going peak values are removed in a like manner by the second MOSFET.