Abstract: A design which allows burn-in of DRAM's at the wafer level, as opposed to in die form or after the package has been assembled. The DRAM dies on the wafer are IEE1149.1 (JTAG) compliant, and the TDO pad of each die is connected to the TDI pad of the next die. The dies are arranged in rows, and each die in a given row is daisy chained to the next die in the row. The last die in the row is daisy chained to the first die in the next row. Additionally, the TMS and TCK pads of the dies are connected in parallel, such as via metal lines running along the scribe area of the wafer. The DRAM dies on the wafer are also connected to power busses along the scribe area so that the individual dies can be powered.

Abstract: An active probe card having integral test circuitry directly attached to the probe card. The probe card includes a circuit board wherein the test circuitry is mounted on the circuit board. In an alternate embodiment, the probe card also includes an on-board signal selection device. The test circuitry applies test signals through probe pins to integrated circuit input pads and samples the test signal responses at integrated circuit output pads. The orientation of the test circuitry attached to the each pin, i.e., input or output, is field programmable. The test circuitry may use boundary scan testing methodology. The active probe card's test circuitry may implement the test methodology of IEEE standard 1149.1 or analog test circuitry to determine the ac and dc parametric characteristics of the integrated circuit. The active probe card may include terminals to which Automatic Test Equipment (ATE) can be attached.