Abstract: Embodiments as disclosed herein provide for methods and systems that give firmware in a given node the ability to control the hardware configuration and activity of every endpoint in every remote node within the array. The standard, inter-node, message passing interconnect and protocol are utilized for this purpose.

Abstract: Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.

Abstract: The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

Abstract: The present technique presents a hardware mechanism by which high performance computational engines utilize external/system memory buffers for data source and sync thus requiring a minimized amount of local buffering and imposing almost no buffer or data size limitations.

Abstract: The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Abstract: The present disclosure provides for methods and systems that give firmware in a given node the ability to control the hardware configuration and activity of every endpoint in every remote node within the array. The standard, inter-node, message passing interconnect and protocol are utilized for this purpose.

Abstract: The present technique presents a hardware mechanism by which high performance computational engines utilize external/system memory buffers for data source and sync thus requiring a minimized amount of local buffering and imposing almost no buffer or data size limitations.

Abstract: Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.

Abstract: The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Abstract: The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

Abstract: A system memory controller and method are disclosed providing a client preemption feature allowing performance optimizations for control firmware in a systolic array. The preemption feature allows clients with very different performance requirements and traffic patterns to share a central memory subsystem with minimal blocking and response latency issues.

Abstract: A scheduler is disclosed. The scheduler can include a time-wheel structure configured to hold scheduling elements, an enqueuer configured to place a scheduling element on the time-wheel structure, and a delay manager configured to direct the scheduling element through the time-wheel structure and remove the scheduling element from the time-wheel structure. The time-wheel structure can include a plurality of decades that can rotate, and each of the plurality of decades can rotate respectively at one or more different rates of rotation. Multiple scheduling elements can be on the time-wheel structure at least partially during the same time. The scheduling elements can be on different decades or on the same decade. One of the plurality of decades can comprise an entry configured to hold a plurality of scheduling elements.

Abstract: A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream.

Abstract: A system and method are presented for digital communication via a time division multiplexed serial data stream. A serial communication system according to the present invention includes a serial communication controller having a set of functional units each configured to perform a specific function of a serial communication protocol. The functional units are operably coupled in series in order to produce digital data according to the serial communication protocol. The set of functional units operates alternately upon an active one of the multiple serial data channels within the time division multiplexed serial data stream. Each functional unit may be a state machine including one or more programmable registers for storing state information which determines the operating state of the functional unit.

Abstract: The present invention provides for an apparatus and a method for performing adaptive frame tracking. The present invention comprises an adaptive frame tracking unit capable of receiving and sending at least one data packet and automatically adjusting a data rate of the data packet by determining if there exists at least one data frame error and correcting for the data frame error in response to a determination that there exists at least one the data frame error.

Abstract: A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint.

Abstract: An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems.

Abstract: A personal information device is provided, which includes an integrated circuit coupled to a variety of peripheral devices. The integrated circuit is configured with a core section and one or more input/output sections. The core section is powered independently of the input/output sections, allowing selective power down of peripheral components coupled to the integrated circuit without the use of external buffers. The input/output sections are configured with unique input/output circuits which perform the buffering task. The integrated circuit is further configured with a partial reset. The partial reset selectively forces portions of the integrated circuit to an initial state while other portions continue to operate. One particular embodiment of the integrated circuit is configured with a CPU and an RTC unit which comprises configuration RAM and a real time clock facility. When the partial reset is activated, the RTC unit is not reset but the CPU is reset.

Abstract: An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems.

Abstract: Within an integrated circuit, an input/output driver circuit is provided. The input/output driver circuit is configured to provide electrical isolation and power savings when the integrated circuit is configured into a computer system such as a personal information device. By providing a mechanism permitting removal of power from the driver circuit, the integrated circuit inhibits current flow from the integrated circuit into a powered-down peripheral device. A force term is activated, when electrical isolation is desired, to inhibit current flow into or from the integrated circuit via an input/output pad voltage level. A power savings is enabled by allowing the power down of peripheral devices coupled to the integrated circuit without the need for external buffer circuits.