Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. An input/output (I/O) mixer including a first multiplier and a second multiplier downconverts a modulated radio frequency wave to an intermediate frequency. The modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal, from a first digital to analog converter (DAC), and a quadrature phase signal, from a second DAC, are input to second inputs of the first multiplier and the second multiplier, respectively. A mixer imbalance between the first mixer and the second mixer is reduced using direct current (DC) bias voltages from the first DAC and the second DAC. The DC bias voltages are determined based on a first and second DAC codes of the first and second DACs. The downconverted modulated radio frequency wave is filtered.

Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. An input/output (I/O) mixer including a first multiplier and a second multiplier downconverts a modulated radio frequency wave to an intermediate frequency. The modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal, from a first digital to analog converter (DAC), and a quadrature phase signal, from a second DAC, are input to second inputs of the first multiplier and the second multiplier, respectively. A mixer imbalance between the first mixer and the second mixer is reduced using direct current (DC) bias voltages from the first DAC and the second DAC. The DC bias voltages are determined based on a first and second DAC codes of the first and second DACs. The downconverted modulated radio frequency wave is filtered.

Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. The electronic device includes a processor configured to: downconvert, by an input/output (I/O) mixer including a first multiplier and a second multiplier, a modulated radio frequency wave to an intermediate frequency, where the modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal and a quadrature phase signal based on a square wave are input to second inputs of the first multiplier and the second multiplier, respectively; filter the downconverted modulated radio frequency wave; and convert the filtered downconverted modulated radio frequency wave to a digital signal.

Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.

Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. The electronic device includes a processor configured to: downconvert, by an input/output (I/O) mixer including a first multiplier and a second multiplier, a modulated radio frequency wave to an intermediate frequency, where the modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal and a quadrature phase signal based on a square wave are input to second inputs of the first multiplier and the second multiplier, respectively; filter the downconverted modulated radio frequency wave; and convert the filtered downconverted modulated radio frequency wave to a digital signal.

Abstract: A method and apparatus is provided. The apparatus a processor configured to generate a first square wave, generate a second square wave, wherein the first square wave and the second square wave are driven by a reference frequency oscillator, modulate a radio frequency wave with the first square wave, downconvert the modulated radio frequency wave to an intermediate frequency, filter the downconverted modulated radio frequency wave, convert the filtered downconverted modulated radio frequency wave to a digital signal, and integrate the digital signal.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: A method and apparatus is provided. The apparatus a processor configured to generate a first square wave, generate a second square wave, wherein the first square wave and the second square wave are driven by a reference frequency oscillator, modulate a radio frequency wave with the first square wave, downconvert the modulated radio frequency wave to an intermediate frequency, filter the downconverted modulated radio frequency wave, convert the filtered downconverted modulated radio frequency wave to a digital signal, and integrate the digital signal.

Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.

Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.

Abstract: A Micro-Electromechanical System (MEMS) recorder is provided. The MEMS recorder includes a scheduler, a serializer, a multiplexer, a transmit/receive switch, a master clock generator, a deserializer, a comparator array to determine whether to generate a signal to wake up a controller and/or a location module from a sleep mode, and a First-In-First-Out (FIFO) memory to output data to be stored and wake up the controller and/or the location module from the sleep mode if a signal to wake up the controller and/or the location module is received or if the FIFO memory is full, wherein the controller and/or the location module is awakened directly by the MEMS recorder or via the controller.

Abstract: A Micro-Electromechanical System (MEMS) recorder is provided. The MEMS recorder includes a scheduler, a serializer, a multiplexer, a transmit/receive switch, a master clock generator, a deserializer, a comparator array to determine whether to generate a signal to wake up a controller and/or a location module from a sleep mode, and a First-In-First-Out (FIFO) memory to output data to be stored and wake up the controller and/or the location module from the sleep mode if a signal to wake up the controller and/or the location module is received or if the FIFO memory is full, wherein the controller and/or the location module is awakened directly by the MEMS recorder or via the controller.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Abstract: Disclosed is a reversible Time Division Duplex (TDD) and/or Time Division Multiple Access (TDMA) radio architecture between Transmission (Tx) and Reception (Rx) functions in a mobile communication system. Accordingly, all of the blocks/components in a Tx/Rx Radio Frequency unit are reversible between Tx and Rx functions. As such, the blocks/components are adapted to bi-directionally process a signal, either in a Tx or Rx direction, based on switching.

Abstract: GPS navigation devices or GPS receivers can consume less power by using a temperature recorder circuit and/or a power manager in calculating the accuracies of the GPS system time and reference frequency to improve battery life. A representative receiver includes a time reference device that generates data associated with a GPS system time, and a temperature recorder circuit that operates using the generated data from the time reference device and monitors the temperature of the time reference device while the receiver hibernates. The receiver further includes memory including a power manager that has instructions, which are processed by a processing device after the receiver wakes up. The instructions associated with the power manager include determining if the temperature recorder circuit sent a wake-up signal, reading data from the temperature recorder circuit, and adjusting parameters associated with at least one of the following: the time reference device and the temperature recorder circuit.

Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.