Patents by Inventor Daniel Ballegeer

Daniel Ballegeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11741024
    Abstract: A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Leon Zlotnik, Jeremy Anderson, Lev Zlotnik, Daniel Ballegeer
  • Publication number: 20210157750
    Abstract: A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.
    Type: Application
    Filed: August 17, 2020
    Publication date: May 27, 2021
    Applicant: Intel Corporation
    Inventors: Leon Zlotnik, Jeremy Anderson, Lev Zlotnik, Daniel Ballegeer