Patents by Inventor Daniel Barnard
Daniel Barnard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12620162Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.Type: GrantFiled: January 8, 2024Date of Patent: May 5, 2026Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Patent number: 12592023Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements for intersection testing. The system defines and updates progress information that identifies, for a ray, leaf nodes of the hierarchical acceleration structure which identify elements for which it is not yet known whether or not the ray interests.Type: GrantFiled: January 29, 2024Date of Patent: March 31, 2026Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Patent number: 12579728Abstract: Ray tracing systems and methods are described for processing rays. A parent shader is executed for a ray. The parent shader includes a shader recursion instruction which invokes a child shader. The execution of the parent shader for the ray is suspended. Intermediate data for the parent shader is stored in a heap of memory, wherein the intermediate data comprises state data and payload data. Storing intermediate data comprises allocating a first set of registers in the heap of memory for storing payload data, and allocating a second set of registers in the heap of memory for storing state data. When the parent shader is ready to resume, intermediate data for the parent shader is read from the heap of memory, and the execution of the parent shader for the ray is resumed.Type: GrantFiled: September 24, 2021Date of Patent: March 17, 2026Assignee: Imagination Technologies LimitedInventors: Daniel Barnard, Alistair Goudie
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Patent number: 12511812Abstract: Shader processing units for a graphics processing unit that are configured to execute one or more ray tracing shaders that process ray data associated with one or more rays. The ray data for a ray includes a plurality of ray data elements. The shader processing unit comprises storage, and load logic. The load logic is configured to receive, as part of a ray tracing shader, a ray load instruction that comprises: (i) information identifying a load group of a plurality of load groups, each load group of the plurality of load groups comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified load group to be retrieved from an external unit. In response to the ray load instruction, the load logic sends one or more load requests to the external unit which cause the external unit to retrieve the identified ray data elements of the identified load group for one or more rays.Type: GrantFiled: March 26, 2023Date of Patent: December 30, 2025Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Publication number: 20250321791Abstract: A method of managing resources in a GPU comprises allocating a region of off-chip storage to a geometry task on creation of the geometry task and receiving, at an on-chip store in the GPU, a memory allocation request for the geometry task from a shader core in the GPU, wherein the memory allocation request is received after generation of geometry data for the geometry task. In response to receiving the memory allocation request, the method comprises determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task. In response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on-chip store and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off-chip storage.Type: ApplicationFiled: February 3, 2025Publication date: October 16, 2025Inventors: Ian King, Daniel Barnard
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Publication number: 20250278605Abstract: Hardware logic for implementing a convolutional neural network (CNN) is configured to receive input data values to be processed in a layer of the CNN. Addresses in banked memory of a buffer in which the received input data values are to be stored are determined based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer, wherein the format parameter of the filter comprises a stride. The received input data values are then stored at the determined addresses in the buffer for retrieval for processing in the layer.Type: ApplicationFiled: May 20, 2025Publication date: September 4, 2025Inventors: Daniel Barnard, Clifford Gibson, Colin McQuillan
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Publication number: 20250225711Abstract: Shader processing units for a graphics processing unit execute ray tracing shaders that generate ray data associated with rays. The ray data includes a plurality of ray data elements. Store logic receives, as part of a ray tracing shader, a ray store instruction that includes: (i) information identifying a store group of a plurality of store groups, each store group comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified store group to be stored in an external unit. In response to receiving the ray store instruction, the store logic retrieves the identified ray data elements for one or more rays from the storage. The store logic then sends one or more store requests to an external unit which cause the external unit to store the identified ray data elements for the one or more rays.Type: ApplicationFiled: March 25, 2025Publication date: July 10, 2025Inventor: Daniel Barnard
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Publication number: 20250173951Abstract: A ray tracing unit and method for processing a ray in a ray tracing system performs intersection testing for the ray by performing one or more intersection testing iterations. Each intersection testing iteration includes: (i) traversing an acceleration structure to identify the nearest intersection of the ray with a primitive that has not been identified as the nearest intersection in any previous intersection testing iterations for the ray; and (ii) if, based on a characteristic of the primitive, a traverse shader is to be executed in respect of the identified intersection: executing the traverse shader in respect of the identified intersection; and if the execution of the traverse shader determines that the ray does not intersect the primitive at the identified intersection, causing another intersection testing iteration to be performed. When the intersection testing for the ray is complete, an output shader is executed to process a result of the intersection testing for the ray.Type: ApplicationFiled: January 30, 2025Publication date: May 29, 2025Inventors: Daniel Barnard, Mike Livesley, Gregory Clark
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Publication number: 20250156678Abstract: Input data for a convolutional neural network (CNN) is stored in a buffer comprising a plurality of banks, by receiving input data comprising input data values to be processed in the CNN, determining addresses in the buffer in which the received input data values are to be stored, keeping a cursor for one or more salient positions to reduce arithmetic performed to determine the addresses in the buffer in which the received input data values are to be stored, and storing the received input data values at the determined addresses in the buffer.Type: ApplicationFiled: January 16, 2025Publication date: May 15, 2025Inventors: Daniel Barnard, Clifford Gibson, Colin McQuillan
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Patent number: 12277488Abstract: A method for providing input data for a layer of a convolutional neural network (CNN). Input data is received comprising input data values to be processed in a layer of the CNN. Addresses in banked memory of a buffer are determined in which the received data values are to be stored based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer. The received input data values are stored at the determined addresses in the buffer for retrieval for processing in the layer.Type: GrantFiled: July 19, 2022Date of Patent: April 15, 2025Assignee: Imagination Technologies LimitedInventors: Daniel Barnard, Clifford Gibson, Colin McQuillan
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Patent number: 12277641Abstract: Shader processing units for a graphics processing unit that are configured to execute one or more ray tracing shaders that generate ray data associated with one or more rays. The ray data for a ray includes a plurality of ray data elements. The shader processing unit comprises local storage, and store logic. The store logic is configured to receive, as part of a ray tracing shader, a ray store instruction that comprises: (i) information identifying a store group of a plurality of store groups, each store group of the plurality of store groups comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified store group to be stored in an external unit). In response to receiving the ray store instruction, the store logic retrieves the identified ray data elements for one or more rays from the storage.Type: GrantFiled: March 26, 2023Date of Patent: April 15, 2025Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Patent number: 12236516Abstract: A ray tracing unit and method for processing a ray in a ray tracing system performs intersection testing for the ray by performing one or more intersection testing iterations. Each intersection testing iteration includes: (i) traversing an acceleration structure to identify the nearest intersection of the ray with a primitive that has not been identified as the nearest intersection in any previous intersection testing iterations for the ray; and (ii) if, based on a characteristic of the primitive, a traverse shader is to be executed in respect of the identified intersection: executing the traverse shader in respect of the identified intersection; and if the execution of the traverse shader determines that the ray does not intersect the primitive at the identified intersection, causing another intersection testing iteration to be performed. When the intersection testing for the ray is complete, an output shader is executed to process a result of the intersection testing for the ray.Type: GrantFiled: June 23, 2022Date of Patent: February 25, 2025Assignee: Imagination Technologies LimitedInventors: Daniel Barnard, Mike Livesley, Gregory Clark
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Publication number: 20240169656Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements for intersection testing. The system defines and updates progress information that identifies, for a ray, leaf nodes of the hierarchical acceleration structure which identify elements for which it is not yet known whether or not the ray interests.Type: ApplicationFiled: January 29, 2024Publication date: May 23, 2024Inventor: Daniel Barnard
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Publication number: 20240144582Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventor: Daniel Barnard
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Patent number: 11887244Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements for intersection testing. The system defines and updates progress information that identifies, for a ray, leaf nodes of the hierarchical acceleration structure which identify elements for which it is not yet known whether or not the ray interests.Type: GrantFiled: December 10, 2021Date of Patent: January 30, 2024Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Patent number: 11868426Abstract: Hardware implementations of, and methods for processing, a convolution layer of a DNN that comprise a plurality of convolution engines wherein the input data and weights are provided to the convolution engines in an order that allows input data and weights read from memory to be used in at least two filter-window calculations performed either by the same convolution engine in successive cycles or by different convolution engines in the same cycle. For example, in some hardware implementations of a convolution layer the convolution engines are configured to process the same weights but different input data each cycle, but the input data for each convolution engine remains the same for at least two cycles so that the convolution engines use the same input data in at least two consecutive cycles.Type: GrantFiled: October 26, 2021Date of Patent: January 9, 2024Assignee: Imagination Technologies LimitedInventors: Chris Martin, David Hough, Clifford Gibson, Daniel Barnard
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Patent number: 11869133Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.Type: GrantFiled: September 30, 2021Date of Patent: January 9, 2024Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Patent number: 11836846Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.Type: GrantFiled: September 30, 2021Date of Patent: December 5, 2023Assignee: Imagination Technologies LimitedInventor: Daniel Barnard
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Publication number: 20230334758Abstract: Shader processing units for a graphics processing unit that are configured to execute one or more ray tracing shaders that generate ray data associated with one or more rays. The ray data for a ray includes a plurality of ray data elements. The shader processing unit comprises local storage, and store logic. The store logic is configured to receive, as part of a ray tracing shader, a ray store instruction that comprises: (i) information identifying a store group of a plurality of store groups, each store group of the plurality of store groups comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified store group to be stored in an external unit). In response to receiving the ray store instruction, the store logic retrieves the identified ray data elements for one or more rays from the storage.Type: ApplicationFiled: March 26, 2023Publication date: October 19, 2023Inventor: Daniel Barnard
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Publication number: 20230334750Abstract: Shader processing units for a graphics processing unit that are configured to execute one or more ray tracing shaders that process ray data associated with one or more rays. The ray data for a ray includes a plurality of ray data elements. The shader processing unit comprises storage, and load logic. The load logic is configured to receive, as part of a ray tracing shader, a ray load instruction that comprises: (i) information identifying a load group of a plurality of load groups, each load group of the plurality of load groups comprising one or more ray data elements of the plurality of ray data elements, and (ii) information identifying one or more ray data elements of the identified load group to be retrieved from an external unit. In response to the ray load instruction, the load logic sends one or more load requests to the external unit which cause the external unit to retrieve the identified ray data elements of the identified load group for one or more rays.Type: ApplicationFiled: March 26, 2023Publication date: October 19, 2023Inventor: Daniel Barnard