Abstract: One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test layout. Next, the system can receive empirical data which is obtained using a process that includes subjecting the test layout to one or more semiconductor manufacturing processes. The system can then receive a set of functions which includes a feature-detecting function, wherein the feature-detecting function's value at an evaluation point is associated with the presence of a particular shape in proximity to the evaluation point. Next, the system can determine the process model using the test layout, the empirical data, and the set of functions.

Abstract: One embodiment provides a method to determine if a pattern is robustly manufacturable. During operation, the system may receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent. Next, the system may determine a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent. The system may then determine if a first semiconductor manufacturing process is capable of robustly manufacturing the second pattern. If the second pattern is not robustly manufacturable, the system may generate an indicator that indicates that the first pattern is not robustly manufacturable.

Abstract: One embodiment of the present invention provides a system that calculates an edge-based proximity correction which is applied to a region in the proximity of an evaluation point. During operation the system receives a layout. Next, the system decomposes polygons in the layout into edges. The system then computes the edge-based proximity correction based on the contributions of the edges. Specifically, the system computes contributions of the edges by: representing an edge as a difference between a first line-segment and a second line-segment which overlap at all points except for the points on the edge; determining a first pre-computed value that represents the first line-segment's contribution to the edge-based proximity correction; determining a second pre-computed value that represents the second line-segment's contribution to the edge-based proximity correction; and determining the contribution of the edge based on the difference between the first pre-computed value and the second pre-computed value.

Abstract: One embodiment of the present invention provides a system that determines a proximity correction for an integrated circuit layout. During operation, the system receives a layout. Next, the system receives an evaluation point within the layout. The system then determines a visible area associated with the evaluation point. Next, the system determines a proximity correction using the visible area.

Abstract: One embodiment of the present invention provides a system that calculates an edge-based proximity correction which is applied to a region in the proximity of an evaluation point. During operation the system receives a layout. Next, the system decomposes polygons in the layout into edges. The system then computes the edge-based proximity correction based on the contributions of the edges. Specifically, the system computes contributions of the edges by: representing an edge as a difference between a first line-segment and a second line-segment which overlap at all points except for the points on the edge; determining a first pre-computed value that represents the first line-segment's contribution to the edge-based proximity correction; determining a second pre-computed value that represents the second line-segment's contribution to the edge-based proximity correction; and determining the contribution of the edge based on the difference between the first pre-computed value and the second pre-computed value.