Abstract: A method for the computer-aided characterization of a circuit comprising a semiconductor layer and a semiconductor component region embedded in the semiconductor layer in an electrically insulated manner, wherein the semiconductor component region is optionally coupled to a dielectric layer structure to be protected, the method comprising determining an indication representing vis-à-vis the semiconductor layer an intensity of an electrical charging of the semiconductor component region by a production process used to produce the circuit, wherein a physical construction of the semiconductor component region is taken into account when determining the indication, and classifying the semiconductor component region taking account of the indication.

Abstract: A method for the computer-aided characterization of a circuit comprising a semiconductor layer and a semiconductor component region embedded in the semiconductor layer in an electrically insulated manner, wherein the semiconductor component region is optionally coupled to a dielectric layer structure to be protected, the method comprising determining an indication representing vis-à-vis the semiconductor layer an intensity of an electrical charging of the semiconductor component region by a production process used to produce the circuit, wherein a physical construction of the semiconductor component region is taken into account when determining the indication, and classifying the semiconductor component region taking account of the indication.

Abstract: A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

Abstract: A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.