Patents by Inventor Daniel Beeler

Daniel Beeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitive sensor integrated onto semiconductor circuit
    Patent number: 9239310
    Abstract: There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an ASIC, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: January 19, 2016
    Assignee: MEAS FRANCE
    Inventors: Jean-Paul Guillemet, Predrag Drljaca, Daniel Beeler, Romuald Gallorini, Vincent Ducere
  • CAPACITIVE SENSOR INTEGRATED ONTO SEMICONDUCTOR CIRCUIT
    Publication number: 20140197500
    Abstract: There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an ASIC, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 17, 2014
    Inventors: Jean-Paul Guillemet, Predrag Drljaca, Daniel Beeler, Romuald Gallorini, Vincent Ducere