Abstract: Multiphase clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as an M-clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted M-clock divided by M. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have a 180°/M relative phase difference. A halt circuit controls the halt multiplexer control to select the gated generated clock when a selected recovered clock matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Abstract: A multiphase clock generating apparatus includes a clock generator providing an M-clock having a frequency M times that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having 1/M the frequency of the M-clock. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have substantially an N•180°/M phase difference from each other, wherein N?1.

Abstract: A multiphase clock generating apparatus includes a clock generator providing an M-clock having a frequency M times that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having 1/M the frequency of the M-clock. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have substantially an N•180°/M phase difference from each other, wherein N?1.

Abstract: Multiphase clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as an M-clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted M-clock divided by M. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have a 180°/M relative phase difference. A halt circuit controls the halt multiplexer control to select the gated generated clock when a selected recovered clock matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Abstract: Quadrature clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as a double clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted double clock divided by two. A recovery circuit recovers first and second clocks having a 90° phase difference from the double clock in accordance with the alignment signal. A halt circuit controls the halt multiplexer control to select the gated generated clock when the alignment signal matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Abstract: A quadrature dock generating apparatus includes a clock generator providing a double clock having a frequency that is twice that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having half the frequency of the double clock. A recovery circuit recovers a first clock and a second clock from the double clock in accordance with the alignment signal. The first and second clocks have substantially a 90° phase difference.

Abstract: A method of testing a logic design in one disclosed embodiment includes identifying a plurality of clocked logic elements of a first logic design. The plurality of logic elements is subdivided into M individual groups of elements. A distinct pseudo-clock is assigned to each of the M groups such that each of the M groups of logic elements is associated with a distinct clock domain in a second logic design. A simulation is performed on the second logic design with the M pseudo-clocks.

Abstract: Quadrature clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as a double clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted double clock divided by two. A recovery circuit recovers first and second clocks having a 90° phase difference from the double clock in accordance with the alignment signal. A halt circuit controls the halt multiplexer control to select the gated generated clock when the alignment signal matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Abstract: A quadrature clock generating apparatus includes a clock generator providing a double clock having a frequency that is twice that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having half the frequency of the double clock. A recovery circuit recovers a first clock and a second clock from the double clock in accordance with the alignment signal. The first and second clocks have substantially a 90° phase difference.

Abstract: The invention includes a method of and an apparatus for testing an integrated circuit which includes simulating the integrated circuit and generating an input vector to and expected output from the integrated circuit. This input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector to yield a first resulting output. A test hardware vector is also created to capture state information pertaining to the integrated circuit. The test hardware vector and the input vector are combined to create a joint input vector and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output.

Abstract: The invention includes a method of and an apparatus for testing an integrated circuit which includes simulating the integrated circuit and generating an input vector to and expected output from the integrated circuit. This input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector to yield a first resulting output. A test hardware vector is also created to capture state information pertaining to the integrated circuit. The test hardware vector and the input vector are combined to create a joint input vector and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output.